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TLV320DAC3202CYZJT Datasheet(PDF) 4 Page - Texas Instruments |
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TLV320DAC3202CYZJT Datasheet(HTML) 4 Page - Texas Instruments |
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4 / 19 page  TLV320DAC3202 SLAS726B – SEPTEMBER 2010 – REVISED MARCH 2012 www.ti.com ELECTRICAL CHARACTERISTICS (continued) AVDD = 3.7 V, DVDD = 1.8 V, TA = 25°C, unless otherwise specified. PARAMETER TEST CONDITIONS MIN TYP MAX UNIT AVDD, GND mode(2) 2 DVDD, GND mode(2) 2 Shutdown current µA AVDD, HiZ mode(3) 1 DVDD, HiZ mode(3) 1 From CHIP_EN assertion to Florin reaching Standby Startup time 15.5 ms state (clock and power supplies available) From HSL/R_EN assertion to Florin reaching Active Wake up time state, during which the system is completely 3 ms powered up with headset drivers enabled AUDIO PATH ELECTRICAL PERFORMANCE 0-dB PCM, 1 kHz, THD = 1%, Maximum amplitude at 1.05 Vrms ball 32- Ω load, 4-dB gain 32- Ω load 0.7 Amplitude across load Vrms 16- Ω load 0.45 0.5 Dynamic range 1 kHz, -60 dBFs, A-weighted 97 100 dB (A) POUT = 20 mW 68 1 kHz, 16- Ω load in series THD+N POUT = 12 mW 70 74 dB with 10 Ω (REMI) POUT = 4 mW 72 Frequency response 20 Hz to 20 kHz -0.25 0.25 dB Channel separation 1 kHz, full scale input(4) 90 95 dB PSRR 217 Hz, 500-mVpp ripple on AVDD 80 90 dB Pop noise specification(5) Maximum DC value after power up 0.5 mV RECEIVE CHANNEL DIGITAL FILTER PERFORMANCE, Fs = 44.1 kHz or 48 kHz HPF -3 dB corner 0.8 Hz LPF pass band corner -10 dBFs 5 0.42 Fs Hz frequency LPF pass band ripple -0.25 0.25 dB LPF -3 dB corner 0.48 Fs Hz LPF interpolation 8 multiplier LPF magnitude response < 0.16 Fs -0.05 0.05 dB LPF stop band corner 0.6 Fs Hz frequency LPF stop band < 2 Fs 70 dB attenuation Filter only, at 1 kHz, without HPF Absolute delay 11/ Fs s Excludes interface + compute latency AUDIO INTERFACE TIMING PARAMETERS Tbclk Audio clock period Variable BCLK 1/BCLK ns 0.35 x Tbclkh BCLK high duration BCLK ns period 0.35 x Tbclkl BCLK low duration BCLK ns period Data hold time following Tdv 20 ns BCLK falling edge (2) CHIP_EN = 0, HIZ_L = 0, HIZ_R = 0 (3) CHIP_EN = 0, HIZ_L = 1, HIZ_R = 1 (4) The maximum board resistance should be less than 250 m Ω between the HSOUTL/HSOUTR pins and the HSOUTG pin. (5) Maximum slew rate ( ΔV/Δt) < 5 V/s after A-weighting 4 Submit Documentation Feedback Copyright © 2010–2012, Texas Instruments Incorporated Product Folder Link(s): TLV320DAC3202 |
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