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TMS320F280270PTS Datasheet(PDF) 3 Page - Texas Instruments |
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TMS320F280270PTS Datasheet(HTML) 3 Page - Texas Instruments |
3 / 119 page 3 External Interrupts 16-bit Peripheral Bus SCI (4L FIFO) SPI (4L FIFO) I2C (4L FIFO) Code Security Module GPIO MUX C28x 32-bit CPU A7:0 B7:0 PIE CPU Timer 0 CPU Timer 1 CPU Timer 2 TCK TDI TMS TDO TRST OSC1, OSC2, Ext, PLL, LPM, WD XCLKIN X2 XRS eCAP 32-bit Peripheral Bus COMP1OUT GPIO Mux LPM Wakeup AIO MUX ADC PSWD FLASH 8K/16K x 16 Secure OTP 1K x 16 Secure OTP/Flash Wrapper M0 SARAM 1K x 16 (0-wait) M1 SARAM 1K x 16 (0-wait) Boot-ROM 8K x 16 (0-wait) SARAM 1K/2K x 16 (0-wait) Secure COMP COMP1A COMP1B COMP2A COMP2B COMP2OUT X1 GPIO MUX VREG POR/ BOR Memory Bus Memory Bus ePWM 32-Bit Peripheral Bus From COMP1OUT, COMP2OUT TMS320F280270, TMS320F280260 TMS320F280230, TMS320F280220 www.ti.com SPRS810 – APRIL 2012 1.3 Functional Block Diagram A. Not all peripheral pins are available at the same time due to multiplexing. Figure 1-1. Functional Block Diagram Copyright © 2012, Texas Instruments Incorporated TMS320F2802x0 ( Piccolo™) MCUs 3 Submit Documentation Feedback Product Folder Link(s): TMS320F280270 TMS320F280260 TMS320F280230 TMS320F280220 |
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