UCC27518

UCC27519

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SLUSB33 – MAY 2012

ABSOLUTE MAXIMUM RATINGS

(1) (2) (3)

over operating free-air temperature range (unless otherwise noted)

MIN

MAX

UNIT

Supply voltage range

VDD

-0.3

20

V

OUT voltage

-0.3

VDD + 0.3

Output continuous current

0.3

A

Output pulsed current (0.5 µs)

4

-0.3

20

Human Body Model, HBM

2000

V

ESD

Charged Device Model, CDM SOT-

500

23

-40

150

-65

150

°C

Soldering, 10 sec.

300

Lead temperature

Reflow

260

(1)

Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings

only and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating

conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

(2)

All voltages are with respect to GND unless otherwise noted. Currents are positive into, negative out of the specified terminal. See

Packaging Section of the datasheet for thermal limitations and considerations of packages.

(3)

These devices are sensitive to electrostatic discharge; follow proper device handling procedures.

(4)

Maximum voltage on input pins is not restricted by the voltage on the VDD pin.

THERMAL INFORMATION

UCC27518

UCC27519

THERMAL METRIC

SOT-23 DBV

UNITS

5 PINS

5 PINS

217.6

217.6

85.8

85.8

44.0

44.0

°C/W

4.0

4.0

43.2

43.2

(1)

For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.

(2)

The junction-to-ambient thermal resistance under natural convection is obtained in a simulation on a JEDEC-standard, high-K board, as

specified in JESD51-7, in an environment described in JESD51-2a.

(3)

The junction-to-case (top) thermal resistance is obtained by simulating a cold plate test on the package top. No specific JEDEC-

standard test exists, but a close description can be found in the ANSI SEMI standard G30-88.

(4)

The junction-to-board thermal resistance is obtained by simulating in an environment with a ring cold plate fixture to control the PCB

temperature, as described in JESD51-8.

(5)

The junction-to-top characterization parameter,

from the simulation data for obtaining

(6)

The junction-to-board characterization parameter,

from the simulation data for obtaining

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