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AMS73CAG01408RALJH8H Datasheet(PDF) 1 Page - Advanced Monolithic Systems Ltd |
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AMS73CAG01408RALJH8H Datasheet(HTML) 1 Page - Advanced Monolithic Systems Ltd |
1 / 31 page 1 AMS73CAG01808RA HIGH PERFORMANCE 1Gbit DDR3 SDRAM 8 BANKS X 16Mbit X 8 AMS73CAG01808RA Rev.1.0 December 2010 - H7 - I9 DDR3-1066 DDR3-1333 Clock Cycle Time ( tCK6, CWL=5 ) 2.5 ns 2.5 ns Clock Cycle Time ( tCK7, CWL=6 ) 1.875 ns 1.875 ns Clock Cycle Time ( tCK8, CWL=6 ) 1.875 ns 1.875 ns Clock Cycle Time ( tCK9, CWL=7 ) - 1.5 ns Clock Cycle Time ( tCK10, CWL=7 ) - 1.5 ns System Frequency (fCK max) 533 MHz 667 MHz Specifications - Density : 1G bits - Organization : 16M words x 8 bits x 8 banks - Package : - 78-ball FBGA - Lead-free (RoHS compliant) and Halogen-free - Power supply : VDD, VDDQ = 1.5V ± 0.075V - Data rate : 1333Mbps/1066Mbps (max.) - 1KB page size - Row address: A0 to A13 - Column address: A0 to A9 - Eight internal banks for concurrent operation - Interface : SSTL_15 - Burst lengths (BL) : 8 and 4 with Burst Chop (BC) - Burst type (BT) : - Sequential (8, 4 with BC) - Interleave (8, 4 with BC) - CAS Latency (CL) : 5, 6, 7, 8, 9, 10, 11 - CAS Write Latency (CWL) : 5, 6, 7, 8 - Precharge : auto precharge option for each burst ac- cess - Driver strength : RZQ/7, RZQ/6 (RZQ = 240 Ω) - Refresh : auto-refresh, self-refresh - Refresh cycles : - Average refresh period 7.8 μs at 0°C ≤ Tc ≤ +85°C 3.9 μs at +85°C < Tc ≤ +95°C - Operating case temperature range - Tc = 0°C to +95°C Features - Double-data-rate architecture; two data transfers per clock cycle - The high-speed data transfer is realized by the 8 bits prefetch pipelined architecture - Bi-directional differential data strobe (DQS and DQS) is transmitted/received with data for capturing data at the receiver - DQS is edge-aligned with data for READs; center- aligned with data for WRITEs - Differential clock inputs (CK and CK) - DLL aligns DQ and DQS transitions with CK transitions - Commands entered on each positive CK edge; data and data mask referenced to both edges of DQS - Data mask (DM) for write data - Posted CAS by programmable additive latency for bet- ter command and data bus efficiency - On-Die Termination (ODT) for better signal quality - Synchronous ODT - Dynamic ODT - Asynchronous ODT - Multi Purpose Register (MPR) for pre-defined pattern read out - ZQ calibration for DQ drive and ODT - Programmable Partial Array Self-Refresh (PASR) - RESET pin for Power-up sequence and reset function - SRT range : Normal/extended - Programmable Output driver impedance control Device Usage Chart Operating Temperature Range Package Outline Speed Power Temperature Mark 78-ball FBGA - H7 - I9 Std. L 0°C ≤ Tc ≤ 95°C • •••• Blank -40°C ≤ Tc ≤ 95°C • •••• I AMS73CAG01808RA |
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