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LTC1407A Datasheet(PDF) 1 Page - Linear Technology |
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LTC1407A Datasheet(HTML) 1 Page - Linear Technology |
1 / 22 page LTC1403-1/LTC1403A-1 1 14031fc BLOCK DIAGRAM FEATURES DESCRIPTION Serial 12-Bit/14-Bit, 2.8Msps Sampling ADCs with Shutdown APPLICATIONS n 2.8Msps Conversion Rate n Low Power Dissipation: 14mW n 3V Single Supply Operation n 2.5V Internal Bandgap Reference can be Overdriven n 3-Wire Serial Interface n Sleep (10µW) Shutdown Mode n Nap (3mW) Shutdown Mode n 80dB Common Mode Rejection n ±1.25V Bipolar Input Range n Tiny 10-Lead MSE Package n Communications n Data Acquisition Systems n Uninterrupted Power Supplies n Multiphase Motor Control n Multiplexed Data Acquisition The LTC®1403-1/LTC1403A-1 are 12-bit/14-bit, 2.8Msps serial ADCs with differential inputs. The devices draw only 4.7mA from a single 3V supply and come in a tiny 10-lead MSE package. A Sleep shutdown feature lowers power consumption to 10µW. The combination of speed, low powerandtinypackagemakestheLTC1403-1/LTC1403A-1 suitable for high speed, portable applications. The 80dB common mode rejection allows users to elimi- nate ground loops and common mode noise by measuring signals differentially from the source. The devices convert –1.25V to 1.25V bipolar inputs differentially. The absolute voltage swing for AIN+ and AIN– extends from ground to the supply voltage. Theserialinterfacesendsouttheconversionresultsduring the16clockcyclesfollowingCONV↑forcompatibilitywith standard serial interfaces. If two additional clock cycles for acquisition time are allowed after the data stream in between conversions, the full sampling rate of 2.8Msps can be achieved with a 50.4MHz clock. L , LT, LTC, LTM, Linear Technology and the Linear logo are registered trademarks and SoftSpan is a trademark of Linear Technology Corporation. All other trademarks are the property of their respective owners. 14031 TA01a – + 1 2 7 3 4 S & H GND EXPOSED PAD LTC1403A-1 VREF 10µF AIN– AIN+ 14-BIT ADC 3V 10µF 14 8 10 9 THREE- STATE SERIAL OUTPUT PORT 2.5V REFERENCE TIMING LOGIC VDD SDO CONV SCK 5 6 11 THD, 2nd and 3rd vs Input Frequency for Differential Input Signals FREQUENCY (MHz) 0.1 –80 –74 –68 –62 –56 1 10 100 14031 TA01b –86 –92 –98 –104 –50 –44 THD 3rd 2nd |
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