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LTC5557 Datasheet(PDF) 1 Page - Linear Technology |
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LTC5557 Datasheet(HTML) 1 Page - Linear Technology |
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1 / 36 page  1 2188f LTC2188 Typical applicaTion FeaTures applicaTions DescripTion 16-Bit, 20Msps Low Power Dual ADC n Communications n Cellular Base Stations n Software Defined Radios n Portable Medical Imaging n Multi-Channel Data Acquisition n Nondestructive Testing n Two-Channel Simultaneously Sampling ADC n 77dB SNR n 90dB SFDR n Low Power: 76mW Total, 38mW per Channel n Single 1.8V Supply n CMOS, DDR CMOS, or DDR LVDS Outputs n Selectable Input Ranges: 1VP-P to 2VP-P n 550MHz Full Power Bandwidth S/H n Optional Data Output Randomizer n Optional Clock Duty Cycle Stabilizer n Shutdown and Nap Modes n Serial SPI Port for Configuration n 64-Lead (9mm × 9mm) QFN Package The LTC®2188 is a two-channel simultaneous sampling 16-bitA/Dconverterdesignedfordigitizinghighfrequency, wide dynamic range signals. It is perfect for demanding communications applications with AC performance that includes77dBSNRand90dBspuriousfreedynamicrange (SFDR).Ultralowjitterof0.07psRMSallowsundersampling of IF frequencies with excellent noise performance. DC specs include ±2LSB INL (typ), ±0.5LSB DNL (typ) and no missing codes over temperature. The transition noise is 3.2LSBRMS. The digital outputs can be either full rate CMOS, Double Data Rate CMOS, or Double Data Rate LVDS. A separate output power supply allows the CMOS output swing to range from 1.2V to 1.8V. The ENC+ and ENC– inputs may be driven differentially or single-ended with a sine wave, PECL, LVDS, TTL, or CMOS inputs. An optional clock duty cycle stabilizer al- lows high performance at full speed for a wide range of clock duty cycles. L , LT, LTC, LTM, Linear Technology and the Linear logo are registered trademarks of Linear Technology Corporation. All other trademarks are the property of their respective owners. Integral Non-Linearity (INL) CMOS, DDR CMOS OR DDR LVDS OUTPUTS 1.8V VDD 1.8V OVDD CLOCK CONTROL D1_15 D1_0 2188 TA01a CH 1 ANALOG INPUT OUTPUT DRIVERS • • • GND OGND S/H 16-BIT ADC CORE CH 2 ANALOG INPUT S/H 16-BIT ADC CORE D2_15 D2_0 • • • 20MHz CLOCK OUTPUT CODE 0 –4.0 –3.0 –2.0 –1.0 0 1.0 4.0 3.0 2.0 16384 32768 49152 65536 2188 TA01b |
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