LTC6421-20 datasheet(7/36 Pages) LINER

Part #	LTC6421-20

Description	16-Bit, 20Msps Low Power Dual ADC

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Manufacturer	LINER [Linear Technology]

Direct Link	http://www.linear.com

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7

2188f

LTC2188

power requireMenTs The

l

denotes the specifications which apply over the full operating temperature

range, otherwise specifications are at TA = 25°C. (Note 9)

SYMBOL PARAMETER

CONDITIONS

MIN

TYP

MAX

UNITS

CMOS Output Modes: Full Data Rate and Double Data Rate

VDD

Analog Supply Voltage

(Note 10)

l

1.7

1.8

1.9

V

OVDD

Output Supply Voltage

(Note 10)

l

1.1

1.8

1.9

V

IVDD

Analog Supply Current

DC Input

Sine Wave Input

l

42

43

50

mA

IOVDD

Digital Supply Current

Sine Wave Input, OVDD = 1.2V

1.6

mA

PDISS

Power Dissipation

DC Input

Sine Wave Input, OVDD = 1.2V

l

75.6

79.3

90

mW

LVDS Output Mode

VDD

Analog Supply Voltage

(Note 10)

l

1.7

1.8

1.9

V

OVDD

Output Supply Voltage

(Note 10)

l

1.7

1.8

1.9

V

IVDD

Analog Supply Current

Sine Input, 1.75mA Mode

Sine Input, 3.5mA Mode

l

45

47

54

mA

IOVDD

Digital Supply Current

(0VDD = 1.8V)

Sine Input, 1.75mA Mode

Sine Input, 3.5mA Mode

l

38

74

83

mA

PDISS

Power Dissipation

Sine Input, 1.75mA Mode

Sine Input, 3.5mA Mode

l

149

218

247

mW

All Output Modes

PSLEEP

Sleep Mode Power

1

mW

PNAP

Nap Mode Power

10

mW

PDIFFCLK Power Increase with Differential Encode Mode Enabled

(No increase for Nap or Sleep Modes)

20

mW

TiMing characTerisTics The

l

denotes the specifications which apply over the full operating temperature

range, otherwise specifications are at TA = 25°C. (Note 5)

SYMBOL PARAMETER

CONDITIONS

MIN

TYP

MAX

UNITS

fS

Sampling Frequency

(Note 10)

l

1

20

MHz

tL

ENC Low Time (Note 8)

Duty Cycle Stabilizer Off

Duty Cycle Stabilizer On

l

20

2

25

500

ns

tH

ENC High Time (Note 8)

Duty Cycle Stabilizer Off

Duty Cycle Stabilizer On

l

20

2

25

500

ns

tAP

Sample-and-Hold Acquisition Delay Time

0

ns

SYMBOL PARAMETER

CONDITIONS

MIN

TYP

MAX

UNITS

Digital Data Outputs (CMOS Modes: Full Data Rate and Double Data Rate)

tD

ENC to Data Delay

CL = 5pF (Note 8)

l

1.1

1.7

3.1

ns

tC

ENC to CLKOUT Delay

CL = 5pF (Note 8)

l

1

1.4

2.6

ns

tSKEW

DATA to CLKOUT Skew

tD – tC (Note 8)

l

0

0.3

0.6

ns

Pipeline Latency

Full Data Rate Mode

Double Data Rate Mode

6

6.5

Cycles

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LTC6421-20 Datasheet(PDF) 7 Page - Linear Technology

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