EBJ41UF8BCS0

Data Sheet E1670E30 (Ver. 3.0)

4

Pin Description

Pin name

Function

A0 to A14

Address input

Row address

A0 to A14

Column address

A0 to A9

A10 (AP)

Auto precharge

A12 (/BC)

Burst chop

BA0, BA1, BA2

Bank select address

/RAS

Row address strobe

/CAS

Column address strobe

/WE

Write enable

/CS0, /CS1

Chip select

CKE0, CKE1

Clock enable

CK0, CK1

Clock input

/CK0, /CK1

Differential clock input

ODT0, ODT1

ODT control

DQ0 to DQ63

Data input/output

DQS0 to DQS7, /DQS0 to /DQS7

Input and output data strobe

DM0 to DM7

Input mask

SCL

Clock input for serial PD

SDA

Data input/output for serial PD

SA0, SA1

Address input for serial PD

VDD*

1

Power for internal circuit

VDDSPD

Power for serial PD

VREFCA

Reference voltage for CA

VREFDQ

Reference voltage for DQ

VSS

Ground

VTT

I/O termination supply for SDRAM

/RESET

Set DRAM to a known state

NC

No connection

Note: 1. The VDD and VDDQ pins are tied common to a single power-plane on these designs.

1 pin

2 pin

Front side

Back side

71 pin

72 pin

73 pin

74 pin

203 pin

204 pin