EDE5116AJSE-6ELI-E datasheet(8/76 Pages) ELPIDA

Part #	EDE5116AJSE-6ELI-E

Description	512M bits DDR2 SDRAM

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Manufacturer	ELPIDA [Elpida Memory]

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EDE5116AJSE-LI

Data Sheet E1171E40 (Ver. 4.0)

8

DC Characteristics 1 (TC =

−40°C to +95°C, VDD, VDDQ = 1.8V ± 0.1V)

Parameter

Symbol

Grade

max.

Unit

Test condition

Operating current

(ACT-PRE)

IDD0

65

mA

one bank; tCK = tCK (IDD), tRC = tRC (IDD),

tRAS = tRAS min.(IDD);

CKE is H, /CS is H between valid commands;

Address bus inputs are SWITCHING;

Data bus inputs are SWITCHING

Operating current

(ACT-READ-PRE)

IDD1

80

mA

one bank; IOUT = 0mA;

BL = 4, CL = CL(IDD), AL = 0;

tCK = tCK (IDD), tRC = tRC (IDD),

tRAS = tRAS min.(IDD); tRCD = tRCD (IDD);

CKE is H, /CS is H between valid commands;

Address bus inputs are SWITCHING;

Data pattern is same as IDD4W

Precharge power-down

standby current

IDD2P

10

mA

all banks idle; tCK = tCK (IDD); CKE is L;

Other control and address bus inputs are STABLE;

Data bus inputs are FLOATING

Precharge quiet

standby current

IDD2Q

15

mA

all banks idle; tCK = tCK (IDD);

CKE is H, /CS is H;

Other control and address bus inputs are STABLE;

Data bus inputs are FLOATING

Idle standby current

IDD2N

20

mA

all banks idle; tCK = tCK (IDD);

CKE is H, /CS is H;

Other control and address bus inputs are SWITCHING;

Data bus inputs are SWITCHING

IDD3P-F

15

mA

Fast PDN Exit

MRS(12) = 0

Active power-down

standby current

IDD3P-S

12

mA

all banks open;

tCK = tCK (IDD);

CKE is L;

Other control and

address bus inputs

are STABLE;

Data bus inputs

are FLOATING

Slow PDN Exit

MRS(12) = 1

Active standby current

IDD3N

35

mA

all banks open;

tCK = tCK (IDD), tRAS = tRAS max.(IDD),

tRP = tRP (IDD);

CKE is H, /CS is H between valid commands;

Other control and address bus inputs are SWITCHING;

Data bus inputs are SWITCHING

Operating current

(Burst read operating)

IDD4R

145

mA

all banks open, continuous burst reads,

IOUT = 0mA; BL = 4, CL = CL(IDD), AL = 0;

tCK = tCK (IDD),

tRAS = tRAS max.(IDD), tRP = tRP (IDD);

CKE is H, /CS is H between valid commands;

Address bus inputs are SWITCHING;

Data pattern is same as IDD4W

Operating current

(Burst write operating)

IDD4W

140

mA

all banks open, continuous burst writes;

BL = 4, CL = CL(IDD), AL = 0;

tCK = tCK (IDD),

tRAS = tRAS max.(IDD), tRP = tRP (IDD);

CKE is H, /CS is H between valid commands;

Address bus inputs are SWITCHING;

Data bus inputs are SWITCHING

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