EDE5116AHBG-8E-E datasheet(7/75 Pages) ELPIDA

Part #	EDE5116AHBG-8E-E

Description	512M bits DDR2 SDRAM

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Manufacturer	ELPIDA [Elpida Memory]

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EDE5108AHBG, EDE5116AHBG

Preliminary Data Sheet E0933E30 (Ver. 3.0)

7

DC Characteristics 1 (TC = 0

°C to +85°C, VDD, VDDQ = 1.8V ± 0.1V)

×8

×16

Parameter

Symbol

Grade

max.

Unit

Test condition

Operating current

(ACT-PRE)

IDD0

-8E, -8G

-6E

-5C

-4A

75

70

65

60

90

85

80

75

mA

one bank; tCK = tCK (IDD), tRC = tRC (IDD),

tRAS = tRAS min.(IDD);

CKE is H, /CS is H between valid commands;

Address bus inputs are SWITCHING;

Data bus inputs are SWITCHING

Operating current

(ACT-READ-PRE)

IDD1

-8E, -8G

-6E

-5C

-4A

85

80

75

70

105

100

90

85

mA

one bank; IOUT = 0mA;

BL = 4, CL = CL(IDD), AL = 0;

tCK = tCK (IDD), tRC = tRC (IDD),

tRAS = tRAS min.(IDD); tRCD = tRCD (IDD);

CKE is H, /CS is H between valid commands;

Address bus inputs are SWITCHING;

Data pattern is same as IDD4W

Precharge power-

down standby

current

IDD2P

-8E, -8G

-6E

-5C

-4A

10

8

10

8

mA

all banks idle; tCK = tCK (IDD); CKE is L;

Other control and address bus inputs are

STABLE;

Data bus inputs are FLOATING

Precharge quiet

standby current

IDD2Q

-8E, -8G

-6E

-5C

-4A

28

25

22

20

28

25

22

20

mA

all banks idle; tCK = tCK (IDD);

CKE is H, /CS is H;

Other control and address bus inputs are

STABLE;

Data bus inputs are FLOATING

Idle standby current

IDD2N

-8E, -8G

-6E

-5C

-4A

35

30

25

20

35

30

25

20

mA

all banks idle; tCK = tCK (IDD);

CKE is H, /CS is H;

Other control and address bus inputs are

SWITCHING;

Data bus inputs are SWITCHING

IDD3P-F

-8E, -8G

-6E

-5C

-4A

25

20

15

25

20

15

mA

Fast PDN Exit

MRS(12) = 0

Active power-down

standby current

IDD3P-S

-8E, -8G

-6E

-5C

-4A

15

13

15

13

mA

all banks open;

tCK = tCK (IDD);

CKE is L;

Other control and

address bus inputs

are STABLE;

Data bus inputs

are FLOATING

Slow PDN Exit

MRS(12) = 1

Active standby

current

IDD3N

-8E, -8G

-6E

-5C

-4A

50

45

40

35

50

45

40

35

mA

all banks open;

tCK = tCK (IDD), tRAS = tRAS max.(IDD),

tRP = tRP (IDD);

CKE is H, /CS is H between valid commands;

Other control and address bus inputs are

SWITCHING;

Data bus inputs are SWITCHING

Operating current

(Burst read

operating)

IDD4R

-8E, -8G

-6E

-5C

-4A

135

115

95

75

175

150

125

105

mA

all banks open, continuous burst reads,

IOUT = 0mA; BL = 4, CL = CL(IDD), AL = 0;

tCK = tCK (IDD),

tRAS = tRAS max.(IDD), tRP = tRP (IDD);

CKE is H, /CS is H between valid commands;

Address bus inputs are SWITCHING;

Data pattern is same as IDD4W

Operating current

(Burst write

operating)

IDD4W

-8E, -8G

-6E

-5C

-4A

140

120

100

80

195

170

130

110

mA

all banks open, continuous burst writes;

BL = 4, CL = CL(IDD), AL = 0;

tCK = tCK (IDD),

tRAS = tRAS max.(IDD), tRP = tRP (IDD);

CKE is H, /CS is H between valid commands;

Address bus inputs are SWITCHING;

Data bus inputs are SWITCHING

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