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EDJ8232B5MB-GN-F Datasheet(PDF) 5 Page - Elpida Memory |
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EDJ8232B5MB-GN-F Datasheet(HTML) 5 Page - Elpida Memory |
5 / 142 page EDJ8232B5MB Data Sheet E1825E30 (Ver. 3.0) 5 CONTENTS Specifications.................................................................................................................................................1 Features.........................................................................................................................................................1 Ordering Information......................................................................................................................................2 Part Number ..................................................................................................................................................2 Pin Configurations .........................................................................................................................................3 Block Diagram (DDP) ....................................................................................................................................4 Electrical Conditions ......................................................................................................................................7 Absolute Maximum Ratings ......................................................................................................................... 7 Operating Temperature Condition ............................................................................................................... 7 Recommended DC Operating Conditions (TC = 0 C to +85C, VDD, VDDQ = 1.5V 0.075V) ..................8 AC and DC Input Measurement Levels (TC = 0 C to +85C, VDD, VDDQ = 1.5V 0.075V)......................8 VREF Tolerances ...................................................................................................................................... 10 Input Slew Rate Derating ........................................................................................................................... 11 AC and DC Logic Input Levels for Differential Signals ............................................................................... 16 AC and DC Output Measurement Levels (TC = 0 C to +85C, VDD, VDDQ = 1.5V 0.075V) .................21 AC Overshoot/Undershoot Specification.................................................................................................... 23 Output Driver Impedance........................................................................................................................... 24 On-Die Termination (ODT) Levels and I-V Characteristics ........................................................................26 ODT Timing Definitions.............................................................................................................................. 28 IDD Measurement Conditions (TC = 0 C to +85C, VDD, VDDQ = 1.5V 0.075V) ..................................32 Electrical Specifications...............................................................................................................................45 DC Characteristics 1 (TC = 0 C to +85C, VDD, VDDQ = 1.5V 0.075V) ................................................45 Pin Capacitance (TC = 25 C, VDD, VDDQ = 1.5V 0.075V) ....................................................................47 Standard Speed Bins ................................................................................................................................. 48 AC Characteristics (TC = 0 C to +85C, VDD, VDDQ = 1.5V 0.075V, VSS, VSSQ = 0V)......................50 Block Diagram (Chip) ..................................................................................................................................58 Pin Function.................................................................................................................................................59 Command Operation ...................................................................................................................................61 Command Truth Table ............................................................................................................................... 61 CKE Truth Table ........................................................................................................................................ 65 Simplified State Diagram .............................................................................................................................66 RESET and Initialization Procedure ............................................................................................................67 Power-Up and Initialization Sequence ....................................................................................................... 67 Reset and Initialization with Stable Power ................................................................................................. 68 Programming the Mode Register.................................................................................................................69 Mode Register Set Command Cycle Time (tMRD) ....................................................................................69 MRS Command to Non-MRS Command Delay (tMOD) ............................................................................ 69 DDR3 SDRAM Mode Register 0 [MR0] ..................................................................................................... 70 DDR3 SDRAM Mode Register 1 [MR1] ..................................................................................................... 71 |
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