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EDJ5316DBBG-DJ-F Datasheet(PDF) 5 Page - Elpida Memory

Part # EDJ5316DBBG-DJ-F
Description  512M bits DDR3 SDRAM
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Manufacturer  ELPIDA [Elpida Memory]
Direct Link  http://www.elpida.com/en
Logo ELPIDA - Elpida Memory

EDJ5316DBBG-DJ-F Datasheet(HTML) 5 Page - Elpida Memory

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EDJ5316DBBG
Preliminary Data Sheet E1462E30 (Ver. 3.0)
5
DDR3 SDRAM Mode Register 2 [MR2] ...................................................................................................... 77
DDR3 SDRAM Mode Register 3 [MR3] ...................................................................................................... 78
Burst Length (MR0) .................................................................................................................................... 79
Burst Type (MR0) ....................................................................................................................................... 79
DLL Enable (MR1) ...................................................................................................................................... 80
DLL-off Mode .............................................................................................................................................. 80
DLL on/off switching procedure .................................................................................................................. 81
Additive Latency (MR1)............................................................................................................................... 83
Write Leveling (MR1) .................................................................................................................................. 84
Extended Temperature Usage (MR2) ......................................................................................................... 87
Multi Purpose Register (MR3)..................................................................................................................... 89
Operation of the DDR3 SDRAM..................................................................................................................96
Read Timing Definition................................................................................................................................ 96
Read Operation ........................................................................................................................................ 100
Write Timing Definition.............................................................................................................................. 107
Write Operation......................................................................................................................................... 108
Write Timing Violations ............................................................................................................................. 114
Write Data Mask ....................................................................................................................................... 115
Precharge ................................................................................................................................................. 116
Auto Precharge Operation ........................................................................................................................ 117
Auto-Refresh............................................................................................................................................. 118
Self-Refresh.............................................................................................................................................. 119
Power-Down Mode ................................................................................................................................... 120
Input Clock Frequency Change during Precharge Power-Down............................................................... 127
On-Die Termination (ODT)........................................................................................................................ 128
ZQ Calibration........................................................................................................................................... 140
Addendum: Elpida DDR3 SDRAM Special Feature, Seamless BL4 Access with Bank-Grouping ...........142
Background............................................................................................................................................... 142
Solution..................................................................................................................................................... 144
Seamless BL4 Access with Bank-Grouping Details.................................................................................. 147
AC Specification Comparison Table for Bank-Grouping Feature Enabled/Disabled................................. 152
Timing Diagram with Bank-Grouping Feature Enabled (MR3 bit A11 = 1)................................................ 154
Package Drawing ......................................................................................................................................170
96-ball FBGA ............................................................................................................................................ 170
Recommended Soldering Conditions........................................................................................................171


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