EDW2032BBBG

Data Sheet E1864E10 (Ver. 1.0)

7

1.2

Mirror Function Mode

The GDDR5 SGRAM provides a mirror function (MF) pin to change the physical location of the command, address,

data and WCK pins assisting in routing devices back to back. The MF ball should be tied directly to VSSQ or VDDQ

depending on the control line orientation desired.

The pins affected by this Mirror Function mode are listed in Table 2.

Table 2: Ball Assignment with Mirror Function

Functions within the GDDR5 SGRAM that refer to external signals are transparent with respect to Mirror Function

mode, meaning that the signal names shown in the respective functional description apply both to mirrored (MF=1)

and non-mirrored (MF=0) modes. The referenced package pin is determined by the Mirror Function mode the

devices is configured to.

1.3

Clamshell Mode Detection

The GDDR5 SGRAM can operate in a x32 mode or a x16 mode to allow a clamshell configuration with a point to

point connection on the high speed data signals. The disabled pins in x16 mode will be in Hi-Z state, non-terminating.

The x16 mode is detected at power-up on the pin at location C-13 which is EDC1 when configured to MF=0 and

EDC2 when configured to MF=1. For x16 mode this pin is tied to VSSQ; the pin is part of the two bytes that are

disabled in this mode and therefore not needed for EDC functionality. For x32 mode this pin is active and always

terminated to VDDQ in the system or by the controller. The configuration is set with /RESET going high. Once the

configuration has been set, it cannot be changed during normal operation. Usually the configuration is fixed in the

system.

Table 3: Clamshell Mode and Mirror Function

Ball

Signal

Ball

Signal

Ball

Signal

Ball

Signal

MF=0

MF=1

MF=0

MF=1

MF=0

MF=1

MF=0

MF=1

A2

DQ1

DQ25

A4

DQ0

DQ24

K5

A11 A6

A9 A1

G12

/CS

/WE

B2

DQ3

DQ27

B4

DQ2

DQ26

P5

/WCK23 /WCK01

L12

/WE

/CS

C2

EDC0

EDC3

D4

WCK01 WCK23

H10

BA3 A3 BA1 A5

A13

DQ9

DQ17

D2

/DBI0

/DBI3

E4

DQ4

DQ28

K10

BA1 A5 BA3 A3

B13

DQ11

DQ19

E2

DQ5

DQ29

F4

DQ6

DQ30

A11

DQ8

DQ16

C13

EDC1

EDC2

F2

DQ7

DQ31

H4

A10 A0

A8 A7

B11

DQ10

DQ18

D13

/DBI1

/DBI2

M2

DQ31

DQ7

K4

A8 A7

A10 A0

E11

DQ12

DQ20

E13

DQ13

DQ21

N2

DQ29

DQ5

M4

DQ30

DQ6

F11

DQ14

DQ22

F13

DQ15

DQ23

P2

/DBI3

/DBI0

N4

DQ28

DQ4

H11

BA0 A2 BA2 A4

M13

DQ23

DQ15

R2

EDC3

EDC0

P4

WCK23 WCK01

K11

BA2 A4 BA0 A2

N13

DQ21

DQ13

T2

DQ27

DQ3

T4

DQ26

DQ2

M11

DQ22

DQ14

P13

/DBI2

/DBI1

U2

DQ25

DQ1

U4

DQ24

DQ0

N11

DQ20

DQ12

R13

EDC2

EDC1

G3

/RAS

/CAS

D5

/WCK01 /WCK23

T11

DQ18

DQ10

T13

DQ19

DQ11

L3

/CAS

/RAS

H5

A9 A1

A11 A6

U11

DQ16

DQ8

U13

DQ17

DQ9

Mode

MF

EDC1 (MF=0) or EDC2 (MF=1)

x16 non-mirrored

VSSQ

VSSQ

x32 non-mirrored

VSSQ

VDDQ (terminated by the system or controller)

x16 mirrored

VDDQ

VSSQ

x32 mirrored

VDDQ

VDDQ (terminated by the system or controller)