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EN25Q64-104HIP Datasheet(PDF) 5 Page - Eon Silicon Solution Inc. |
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EN25Q64-104HIP Datasheet(HTML) 5 Page - Eon Silicon Solution Inc. |
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5 / 60 page  This Data Sheet may be revised by subsequent versions ©2004 Eon Silicon Solution, Inc., www.eonssi.com or modifications due to changes in technical specifications. 5 EN25Q64 Rev. J, Issue Date: 2011/07/07 Table 1. Pin Names Symbol Pin Name CLK Serial Clock Input DI (DQ0) Serial Data Input (Data Input Output 0) *1 DO (DQ1) Serial Data Output (Data Input Output 1) *1 CS# Chip Enable WP# (DQ2) Write Protect (Data Input Output 2) *2 NC(DQ3) Not Connect (Data Input Output 3) *2 Vcc Supply Voltage (2.7-3.6V) Vss Ground NC No Connect Note: 1. DQ0 and DQ1 are used for Dual and Quad instructions. 2. DQ0 ~ DQ3 are used for Quad instructions. SIGNAL DESCRIPTION Serial Data Input, Output and IOs (DI, DO and DQ0, DQ1, DQ2, DQ3) The EN25Q64 support standard SPI, Dual SPI and Quad SPI operation. Standard SPI instructions use the unidirectional DI (input) pin to serially write instructions, addresses or data to the device on the rising edge of the Serial Clock (CLK) input pin. Standard SPI also uses the unidirectional DO (output) to read data or status from the device on the falling edge CLK. Dual and Quad SPI instruction use the bidirectional IO pins to serially write instruction, addresses or data to the device on the rising edge of CLK and read data or status from the device on the falling edge of CLK. Serial Clock (CLK) The SPI Serial Clock Input (CLK) pin provides the timing for serial input and output operations. ("See SPI Mode") Chip Select (CS#) The SPI Chip Select (CS#) pin enables and disables device operation. When CS# is high the device is deselected and the Serial Data Output (DO, or DQ0, DQ1, DQ2 and DQ3) pins are at high impedance. When deselected, the devices power consumption will be at standby levels unless an internal erase, program or status register cycle is in progress. When CS# is brought low the device will be selected, power consumption will increase to active levels and instructions can be written to and data read from the device. After power-up, CS# must transition from high to low before a new instruction will be accepted. Write Protect (WP#) The Write Protect (WP#) pin can be used to prevent the Status Register from being written. Used in conjunction with the Status Register’s Block Protect (BP0, BP1, BP2 and BP3) bits and Status Register Protect (SRP) bits, a portion or the entire memory array can be hardware protected. The WP# function is only available for standard SPI and Dual SPI operation, when during Quad SPI, this pin is the Serial Data IO (DQ2) for Quad I/O operation. |
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