This Data Sheet may be revised by subsequent versions

©2004 Eon Silicon Solution, Inc., www.eonssi.com

or modifications due to changes in technical specifications.

6

EN71NS032A0

Rev. B, Issue Date: 2011/07/05

Note:

1. With burst mode enabled, CLK must be static(HIGH or LOW) during asynchronous READs and

asynchronous WRITEs and to achieve standby power during standby mode.

2. The WAIT polarity is configured through the bus configuration register (BCR[10]).

3. When LB# and UB# are in select mode (LOW), DQ[15:0] are enabled. When only LB# is in select

mode, DQ[7:0] are enabled. When only UB# is in the select mode, DQ[15:8] are enabled.

4. The device will consume active power in this mode whenever addresses are changed.

5. When the device is in standby mode, address inputs and data inputs/outputs are internally isolated

from any external influence.

6. VIN = VCCQ or 0V; all device pins must be static (unswitched) in order to achieve standby current.

7. DPD is initiated when CE# transitions from LOW to HIGH after writing RCR[4] to 0. DPD is

maintained until CE# transitions from HIGH to LOW.

8. When the BCR is configured for sync mode, sync READ and WRITE, and async READ and WRITE

are supported by ENPSS16

9. Burst mode operation is initialized through the bus configuration register (BCR[15]).

10. Initial cycle. Following cycles are the same as BURST CONTINUE. CE# must stay LOW for the

equivalent of a single-word burst (as indicated by WAIT).

11. X=don’t care. H=logic high. L=logic low.