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MMA1606KW Datasheet(PDF) 9 Page - Freescale Semiconductor, Inc |
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MMA1606KW Datasheet(HTML) 9 Page - Freescale Semiconductor, Inc |
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9 / 45 page  Sensors Freescale Semiconductor, Inc. 9 MMA16xxKW 2.7 Dynamic Electrical Characteristics - DSI VL ≤ (VCC - VSS) ≤ VH, TL ≤ TA ≤ TH, ΔT ≤ 25 K/min, unless otherwise specified # Characteristic Symbol Min Typ Max Units 90 91 92 93 Reset Recovery (See Figure 20) POR negated to 1st DSI Command (Initialization Command) POR negated to Acceleration Data Valid (Including LPF Init) DSI Clear Command to 1st DSI Command (Initialization Command) DSI Clear Command to Acceleration Data Valid (Including LPF Init) tDSI_INIT tDSP_INIT tDSI_INIT tDSP_INIT ⎯ ⎯ ⎯ ⎯ 400 / fOSC ⎯ 400 / fOSC ⎯ ⎯ 10000 / fOSC ⎯ 10000 / fOSC s s s s (7) (7) (7) (7) 94 HCAP Under-Voltage Reset Delay (See Figure 5) VHCAP < VPORHCAP_f to POR assertion tHCAP_POR ⎯ 880 / fOSC ⎯ s(7) 95 VREG Under-Voltage Reset Delay (See Figure 6) VREG < VPORVREG_f to POR assertion tVREG_POR ⎯⎯ 5 μs(3) 96 VREGA Under-Voltage Reset Delay (See Figure 7) VREGA < VPORVREGA_f to POR assertion tVREGA_POR ⎯⎯ 5 μs(3) 97 98 99 VREG, VREGA Capacitor Monitor POR to first Capacitor Test Disconnect Disconnect Time () Disconnect Rate () tPOR_CAPTEST tCAPTEST_TIME tCAPTEST_RATE ⎯ ⎯ ⎯ 12000 / fOSC 6 / fOSC 256 / fOSC ⎯ ⎯ ⎯ s s s (7) (7) (7) 100 Initialization to Bus Switch Closing tBS 89 ⎯ 138 μs(7) 101 BUSOUT Discharge Resistance Activation Time tBUSOUT_Discharge 9.5 10 10.5 μs(3) 102 Communication Data Rate DRATE 100 ⎯ 200 kbps (7) 103 Loss of Signal Reset Time Maximum time below frame threshold tTO 2.00 ⎯ 4.00 ms (7) 104 BUSIN Response Current Slew Rate 1.0 mA to 9.0 mA, 9.0 to 1.0 mA tITR 0.33 ⎯ 10.0 mA/ μs(3) 105 106 BUSIN Timing to Response Current BUSIN Negative Voltage Transition = 3.0V to IRSP = 7.0 mA rise BUSIN Negative Voltage Transition = 3.0V to IRSP = 5.0 mA fall tRSP_R tRSP_F ⎯ ⎯ ⎯ ⎯ 2.50 2.50 μs μs (7) (7) 107 108 DSI BUSIN Signal Duty Cycle Logic ‘0’ Logic ‘1’ * * DCL DCH 10 60 33 67 40 90 % % (7) (7) 109 110 111 112 Inter-frame Separation Time (See Figure 8) Following Read Write NVM Command Following Initialization, BS = 1 Following Initialization, BS = 0 Following other DSI bus commands tIFS tIFS tIFS tIFS 2 200 20 20 ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ms μs μs μs (7) (7) (7) (7) 113 DSI Data Latency tLAT_DSI 4 / fOSC ⎯ 5 / fOSC s(7) 114 Bus Switch Open Time Reset Asserted to ISW_LEAK ≤ 20 μA tBSOPEN ⎯⎯ 500 μs(3) 115 OTP Program Timing Time to program one OTP bit tPROG_BIT 64 ⎯ 256 μs(7) 116 117 118 119 120 121 Self-Test Response Time Self-Test Activation time (EOFSlave to 90% ΔDFLCT_xxx, 180 Hz LPF) Self-Test Deactivation time (EOFSlave to 10% ΔDFLCT_xxx, 180 Hz LPF) Self-Test Activation time (EOFSlave to 90% ΔDFLCT_xxx, 400 Hz LPF) Self-Test Deactivation time (EOFSlave to 10% ΔDFLCT_xxx, 400 Hz LPF) Self-Test Activation time (EOFSlave to 90% ΔDFLCT_xxx, 800 Hz LPF) Self-Test Deactivation time (EOFSlave to 10% ΔDFLCT_xxx, 800 Hz LPF) tST_ACT_180 tST_DEACT_180 tST_ACT_400 tST_DEACT_400 tST_ACT_800 tST_DEACT_800 2.00 2.00 1.00 1.00 0.50 0.50 ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ 5.00 5.00 2.50 2.50 1.75 1.75 ms ms ms ms ms ms (7) (7) (7) (7) (7) (7) 122 Error Detection Response Time Mirror Register CRC Error to Status Flag (S) set (Factory or User Array) tCRC_Err ⎯ 75 / fOSC ⎯ s(7) |
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