EUP7998

DS7998 Ver1.1 Aug. 2010

2

Typical Application Circuit (continued)

Figure 2. For SOP-8(EP) package

Pin Configurations

Package

Type

Pin Configurations

Package

Type

Pin Configurations

TDFN-10

SOP-8

(EP)

Pin Description

PIN

TDFN-10

SOP-8 (EP)

DESCRIPTION

REFIN

1

1

External Reference Input

VLDOIN

2

2

Power Supply of the LDO. Internally connected to the output source

MOSFET.

VO

3

3

Output of the LDO

PGND

4

9

(Thermal pad)

Power Ground

VOSNS

5

4

Voltage sense input for the LDO. Connect to positive terminal of the

output capacitor.

REFOUT

6

5

Buffered Reference Output. The output of the unity-gain reference input

buffer sources and sinks over 10mA. Bypass REFOUT to GND with a

0.1μF ceramic capacitor.

EN

7

6

Enable Control Input. Active High Input. For DDR VTT application,

connect EN to SLP_S3.

GND

8

7

Ground

PGOOD

9

-

Open-Drain Power-Good Output

VIN

10

8

Power Supply Input. Connect to the system supply voltage. Bypass VIN to

GND with a 1μF or 4.7μF ceramic capacitor.

Note(1):PGND, GND and thermal pad must be connected together outside under thermal pad.