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MMA685X Datasheet(PDF) 4 Page - Freescale Semiconductor, Inc |
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MMA685X Datasheet(HTML) 4 Page - Freescale Semiconductor, Inc |
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4 / 52 page  Sensors 4 Freescale Semiconductor, Inc. MMA685x 1 Pin Connections Figure 4. 16-Pin QFN Package, Top View Table 2. Pin Description Pin Pin Name Formal Name Definition 1 VREGA Analog Supply This pin is connected to the power supply for the internal analog circuitry. An external capacitor must be connected between this pin and VSSA. Reference Figure 1. 2 VSS Digital GND This pin is the power supply return node for the digital circuitry. 3 VREG Digital Supply This pin is connected to the power supply for the internal digital circuitry. An external capacitor must be connected between this pin and VSS. Reference Figure 1. 4 VSS Digital GND This pin is the power supply return node for the digital circuitry. 5 N/C No Connect No Connection 6 ARM/ PCM Arm Output / PCM Output The function of this pin is configurable via the DEVCFG register as described in Section 3.1.6.5. When the arming output is selected, ARM can be configured as an open drain, active low output with a pullup current; or an open drain, active high output with a pulldown current. Alternatively, this pin can be configured as a digital output with a PCM signal proportional to the acceleration data. Reference Section 3.8.9 and Section 3.8.10. If unused, this pin must be left unconnected. 7 TEST/ VPP Programming Voltage This pin provides the power for factory programming of the OTP registers. This pin must be connected to VSS in the application. 8 MISO SPI Data Out This pin functions as the serial data output for the SPI port. 9 VCC Supply This pin supplies power to the device. An external capacitor must be connected between this pin and VSS. Reference Figure 1. 10 SCLK SPI Clock This input pin provides the serial clock to the SPI port. An internal pulldown device is connected to this pin. 11 MOSI SPI Data In This pin functions as the serial data input to the SPI port. An internal pulldown device is connected to this pin. 12 CS Chip Select This input pin provides the chip select for the SPI port. An internal pullup device is connected to this pin. 13 VSSA Analog GND This pin is the power supply return node for analog circuitry. 14 N/C No Connect No Connection 15 N/C No Connect No Connection 16 VSSA Analog GND This pin is the power supply return node for analog circuitry. 17 PAD Die Attach Pad This pin is the die attach flag, and is internally connected to VSS. Corner Pads Corner Pads The corner pads are internally connected to VSS. VREGA VSS MOSI SCLK VCC VSS VREG 1 2 3 4 5 6 7 8 12 11 10 9 16 15 14 13 CS 17 |
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