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MMA5248KW Datasheet(PDF) 6 Page - Freescale Semiconductor, Inc |
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MMA5248KW Datasheet(HTML) 6 Page - Freescale Semiconductor, Inc |
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6 / 55 page  Sensors 6 Freescale Semiconductor, Inc. MMA52xxKW 2.3 Electrical Characteristics - Supply and I/O VL ≤ (VCC - VSS) ≤ VH, TL ≤ TA ≤ TH, ΔT ≤ 25 K/min, unless otherwise specified. # Characteristic Symbol Min Typ Max Units 21 Quiescent Supply Current * IIDLE 4.0 — 8.0 mA (1) 22 Modulation Supply Current * IMOD IIDLE+ 22.0 IIDLE+ 26.0 IIDLE+ 30.0 mA (1) 23 Inrush Current (Power On until VBUF, VREG, VREGA Stable) IINRUSH —— 30 mA (3) 24 25 26 Internally Regulated Voltages VBUF VREG VREGA * * * VBUF VREG VREGA 3.60 2.425 2.425 3.80 2.50 2.50 4.00 2.575 2.575 V V V (1) (1) (1) 27 28 29 30 31 32 33 34 Low Voltage Detection Threshold VCC Falling VBUF Falling VREG Falling VREGA Falling Hysteresis VCC VBUF VREG VREGA VVCC_UV_F VBUF_UV_F VREG_UV_F VREGA_UV_F VCC_HYST VBUF_HYST VREG_HYST VREGA_HYST 3.40 2.95 2.15 2.15 0.10 0.05 0.05 0.05 3.70 3.15 2.25 2.25 0.25 0.10 0.10 0.10 4.0 3.35 2.35 2.35 0.40 0.15 0.15 0.15 V V V V V V V V (3, 6) (3, 6) (3, 6) (3, 6) (3) (3) (3) (3) 35 36 External Capacitor (VBUF, VREG, VREGA) Capacitance ESR (including interconnect resistance) ESR 500 0 1000 — 1500 200 nF m Ω (9) (9) 37 38 Synchronization Pulse (Figure 5) VIDLE Voltage Range DC Sync Pulse Detection Threshold * * VIDLE ΔVSYNC — VIDLE+1.4 — VIDLE+2.0 15.4 VIDLE+2.6 V V (3, 11) (3, 6) 39 Sync Pulse Pulldown Current ISYNC_PD —IMOD - IIDLE —mA (3) 40 Output High Voltage (DO) ILoad = 100 μAVOH VREG - 0.1 — — V (9) 41 Output Low Voltage (DO) ILoad = 100 μAVOL —— 0.1 V (9) 42 Input High Voltage CS, SCLK, DI VIH 0.7 * VREG —— V (9) 43 Input Low Voltage CS, SCLK, DI VIL — — 0.3 * VREG V(9) 44 45 Input Current High (at VIH) (DI) Low (at VIL) (CS) IIH IIL -100 10 — — -10 100 μA μA (9) (9) 46 Pulldown Resistance (SCLK) RPD 20 æ 100 k Ω (9) 47 48 Temperature Monitoring Under-Temperature Monitor Threshold Over-Temperature Monitor Threshold TIH TIL — 155 — — -55 — °C °C (9) (9) 49 BUS_SW Output High Voltage (BUS_SW) ILoad = 100 μAVBUS_SW_OH 3.15 — VBUF V(9) 50 Output Low Voltage (BUS_SW) ILoad = 100 μAVBUS_SW_OL 0.0 — 0.45 V (9) 51 Daisy Chain Addressing Mode Sync Pulse Period — tS-S_PM_L —s (7) 52 Bus Switch Output Activation Time (C = 50 pF) From last bit of “SetAdr” Response to 80% of VBUS_SW_OH tBUS_SW — — 300 μs(7) 53 Sync Pulse Blanking Time after “SetAdr” Command Received From last bit of “SetAdr” Response tDC_BLANKING 200000 / fOSC s(7) |
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