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HYB39S16400-1 Datasheet(PDF) 6 Page - Siemens Semiconductor Group |
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HYB39S16400-1 Datasheet(HTML) 6 Page - Siemens Semiconductor Group |
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6 / 19 page  HYB 39S16400/800/160CT-8/-10 16 MBit Synchronous DRAM Semiconductor Group 6 1998-10-01 Block Diagram for HYB 39S16800CT (2 banks × 1M × 8 SDRAM) A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 (BS) CLK Buffer CLK Row Address Counter CS Buffer RAS Buffer CAS Buffer WE Buffer DQM Buffer CS RAS CAS WE DQM Self Refresh Clock CKE Buffer CKE 2048 x 512 Memory Bank A and DQ Gate Sense Amplifiers Row/Column Select Bank A Predecode A Sequential Mode Register Control Bank A Control Predecode B Bank B Sequential Row/Column Bank B Select Row Decoder Data Latches Data Latches and DQ Gate Memory Bank B 2048 x 512 Sense Amplifiers 2048 8 8 12 8 8 8 8 12 11 11 11 3 3 8 8 8 8 2048 DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 8 Column Decoder Column Decoder SPB02836 Row Decoder 512 512 |
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