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F71858 Datasheet(PDF) 11 Page - Feature Integration Technology Inc. |
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F71858 Datasheet(HTML) 11 Page - Feature Integration Technology Inc. |
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11 / 65 page  June, 2009 V0.29P 11 F71858 6. Function Description 6.1 Keyboard Controller The KBC circuit provides the functions included a keyboard and/or a PS/2 mouse, and can be used with IBM®-compatible personal computers or PS/2-based systems. The controller receives serial data from the keyboard or PS/2 mouse, checks the parity of the data, and presents the data to the system as a byte of data in its output buffer. The controller will assert an interrupt to the system when data are placed in its output buffer. Output Buffer The output buffer is an 8-bit read-only register at I/O address 60h. The keyboard controller uses the output buffer to send the scan code received from the keyboard and data bytes required by commands to the system. Input Buffer The input buffer is an 8-bit write-only register at I/O address 60h or 64h. Writing to address 60h sets a flag to indicate a data write; writing to address 64h sets a flag to indicate a command write. Data written to I/O address 60h is sent to keyboard through the controller's input buffer only if the input buffer full bit in the status register is “0”. Status Register The status register is an 8-bit read-only register at I/O address 64h that holds information about the status of the keyboard controller and interface. It may be read at any time. BIT BIT FUNCTION DESCRIPTION 0 Output Buffer Full 0: Output buffer empty 1: Output buffer full 1 Input Buffer Full 0: Input buffer empty 1: Input buffer full 2 System Flag This bit may be set to 0 or 1 by writing to the system flag bit in the command byte of the keyboard controller (KCCB). It defaults to 0 after a power-on reset. 3 Command/Data 0: Data byte 1: Command byte |
Similar Part No. - F71858_09 |
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Similar Description - F71858_09 |
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