SP3483 DS/04

SP3483 Low Power Slew Rate Limited Half-Duplex RS485 Transceivers

© Copyright 2000 Sipex Corporation

4

PIN FUNCTION

Pin 1 – RO – Receiver Output.

Pin 2 – RE – Receiver Output Enable Active LOW.

Pin 3 – DE – Driver Output Enable Active HIGH.

Pin 4 – DI – Driver Input.

Pin 5 – GND – Ground Connection.

Pin 6 – A – Driver Output/Receiver Input

Non-inverting.

Pin 7 – B – Driver Output/Receiver Input Inverting.

Pin 8 – Vcc – Positive Supply +3.00V < V

DESCRIPTION

The SP3483 device is part of a family of +3.3V

low power half-duplex transceivers that meet the

specifications of the RS-485 and RS-422 serial

protocols. The device is pin-to-pin compatible

with the Sipex SP483 device as well as popular

industry standards. The SP3483 features Sipex's

BiCMOS process allowing low power operation

without sacrificing performance.

Drivers

The driver outputs of the SP3483 are differential

outputs meeting the RS-485 and RS-422

standards. The typical voltage output swing

with no load will be 0 Volts to +3.3 Volts.

With a loading of 54

Ω across the differential

outputs, the drivers maintain greater than 1.5V

voltage levels. The drivers have an enable

control line which is active HIGH. A logic

HIGH on DE (pin 3) will enable the differential

driver outputs. A logic LOW on DE (pin 3) will

force the driver outputs into high impedance

(high-Z).

The SP3483 has internally slew rate limited

driver outputs to minimize EMI. The tranceivers

will operate up to 250kbps. The 250mA I

SC

maximum limit on the driver output allows the

SP3483 to withstand an infinite short circuit

over the -7.0V to +12.0V common mode range

without catastrophic damage to the IC.

SP3483

Pinout (Top View)

RO 1

RE 2

DE 3

DI 4

8

7

B

6

A

5

GND

D

R

SP485

Top View

Receivers

The SP3483 receiver has differential inputs with

an input sensitivity as low as

±200mV. Input

impedance of the receivers is typically 15k

Ω

(12k

Ω minimum). A wide common mode range

of -7V to +12V allows for large ground potential

differences between systems. The receiver of

the SP3483 has a high impedance (high-z)

enable control pin. A logic LOW on RE (pin 2)

will enable the receiver, a logic HIGH on RE

(pin 2) will disable the receiver.

The receiver of the SP3483 will operate up to

250kbps. The receiver is equipped with a

fail-safe feature that guarantees the receiver

output will be in a HIGH state when the input

is left unconnected.

Shutdown Mode

The SP3483 is equipped with a Shutdown mode.

To enable the Shutdown state, both the driver

and receiver must be disabled simultaneously.

A logic LOW on DE (pin 3) and a logic HIGH on

RE (pin 2) will put the SP3483 into Shutdown

mode. In Shutdown, supply current will drop to

typical 1

µA, 10µA maximum.