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SP9500KN Datasheet(PDF) 3 Page - Sipex Corporation |
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SP9500KN Datasheet(HTML) 3 Page - Sipex Corporation |
3 / 9 page SP9500DS/04 SP9500 12-Bit, Voltage Output D/A Converter © Copyright 2000 Sipex Corporation 3 SPECIFICATIONS (continued) (Typical at 25˚C; T MIN ≤ TA ≤ TMAX; VDD = +5V, DGND = 0V, VREF = +3.5V; AGND = +1.5V; CMOS logic level digital inputs; specifications apply to all grades unless otherwise noted.) PARAMETER MIN. TYP. MAX. UNITS CONDITIONS POWER REQUIREMENTS Note 5 V DD +5V, ±3%; Note 4, 5 –J, –K 0.22 0.34 mA –A, –B 0.22 0.50 mA Power Dissipation 1.1 mW SWITCHING CHARACTERISTICS CS Setup Time (t CSS)25 ns SCLK Fall to CS Fall Hold Time (t CSH0)20 ns SCLK Fall to CS Rise Hold Time (t CSH1)0 ns SCLK High Width (t CH)40 ns SCLK Low Width (t CL)40 ns DIN Setup Time (t DS)50 ns DIN Hold Time (t DH)0 ns CS High Pulse Width (t CSW)30 ns ENVIRONMENTAL AND MECHANICAL Operating Temperature –J, –K 0 +70 °C –A, –B –40 +85 °C Storage –60 +150 °C Package –_N 8-pin Plastic DIP –_S 8-pin 0.15" SOIC Notes: 1. Integral Linearity, for the SP9500, is measured as the arithmetic mean value of the magnitudes of the greatest positive deviation and the greatest negative deviation from the theoretical value for any given input condition. 2. Differential Linearity is the deviation of an output step from the theoretical value of 1 LSB for any two adjacent digital input codes. 3. 1 LSB = (V REF-AGND)/4,096. 4. V REF = AGND = 2.5V. 5. The following Power up sequence is recommended: VDD (+5V), VREF. |
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