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SP9504 Datasheet(PDF) 6 Page - Sipex Corporation |
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SP9504 Datasheet(HTML) 6 Page - Sipex Corporation |
6 / 11 page SP9504DS/03 SP9504 Quad, 12-Bit, Voltage Output D/A Converter © Copyright 2000 Sipex Corporation 6 A 1 A 0 CS WR1 B1/B2 WR2 XFER CLR FUNCTION 0 0 1 1 X X Address DAC 1 and load input register 0 0 0 1 X X Address DAC 1 and load 4 LSBs 0 1 1 1 X X Address DAC 2 and load input register 0 1 0 1 X X Address DAC 2 and load 4 LSBs 1 0 1 1 X X Address DAC 3 and load input register 1 0 0 1 X X Address DAC 3 and load 4 LSBs 1 1 1 1 X X Address DAC 4 and load input register 1 1 0 1 X X Address DAC 4 and load 4 LSBs X X ** ** X 1 Transfer data from input registers to DAC registers X XXXX 1 Sets all DAC output voltages to 0V X X 1 1 X 0 0 Temporarily force all DAC output voltages to 0V, while CLR is low X X 1 X X X X X Invalid state with any other control line active X X X 1 X X X X Invalid state with any other control line active X = Don’t care; ** = Don’t care; however, CS and WR1 = 1 will inhibit changes to the input registers. To load a 12-bit word to the input register of each DAC, using an 8-bit data bus, the sequence is as follows: 1) Set XFER=1, B1/B2=1, CLR=1, WR1=1, WR2=1, CS=1. 2) Set D11 through D4 to the 8 MSB’s of the desired digital input code. 3) Load the 8 MSB’s of the digital word to the selected input register by cycling WR1 and CS through the “1” — “0” — “1” sequence. 4) Reset B1/B2 from “1” —— “0” 5) Set D11 (MSB) through D8 to the 4 LSB’s of the digital input code. 6) Load the 4 LSB’s by cycling WR1 and CS through the “1” — “0” — “1” sequence. Figure 1. Detailed Block Diagram (only one DAC shown) USING THE SP9504 WITH DOUBLE-BUFFERED INPUTS Loading Data To load a 12-bit word to the input register of each DAC, using a 12-bit data bus, the sequence is as follows: 1) Set XFER=1, B1/B2=1, CLR=1, WR1=1, WR2=1, CS=1. 2) Set A 1 and A0 (the DAC address) to the desired DAC — 0,0 = DAC 1; 0,1 = DAC2 1,0 = DAC 3; 1,1 = DAC4 . 3) Set D11 (MSB) through D0 (LSB) to the desired digital input code. 4) Load the word to the selected DAC by cycling WR1 and CS through the follow- ing sequence: “1” — “0” — “1” 5) Repeat sequence for each input register. DAC 3 TO 7 DECODE & 5 BITS 8–BIT LATCH 4-BIT LATCH DB11 - DB8 DB7 - DB4 Ref In – + VOUT 44 44 4 MUX 4 4 4 8 12 DB3 - DB0 LATCH INPUT REGISTER DAC REGISTER 40 K Ω 40 KΩ Table 2. Control Logic Truth Table 7) Repeat sequence for each input register. |
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