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SP9500JS Datasheet(PDF) 5 Page - Sipex Corporation |
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SP9500JS Datasheet(HTML) 5 Page - Sipex Corporation |
5 / 9 page SP9500DS/04 SP9500 12-Bit, Voltage Output D/A Converter © Copyright 2000 Sipex Corporation 5 VOUT VREF DAC 12 1 SHIFT REGISTER DIN – + – + DIN VREF VOUT VDAC VOUT VDAC VDAC DIN WHERE… = = 4096 x (VREF - AGND) + AGND () LATCH 12 AGND AGND DAC REGISTER DAC REGISTER Figure 1. Detailed Block Diagram USING THE SP9500 External Reference The R-2R DAC input resistance is code depen- dent and is minimum (11k Ω) at code 1365 and 2731. And, it is nearly infinite at code 0. Be- cause of the code-dependent nature of the refer- ence inputs, a high quality, low output imped- ance amplifier should be used to drive the V REF and AGND inputs. Serial Clock and Update Rate The SP9500 maximum serial clock rate (SCLK) is given by 1/(t CH+tCL) which is approximately 12.5 MHz. The digital word update rate is lim- ited by the chip select period, which is 12 X Figure 2. Transfer Function SCLK periods plus the CS high pulse width t CSW. This is equal to a 1 µs or 1 MHz update rate. However, the DAC settling time to 12–Bits is 7.5 µs, which for full scale output transitions would limit the update rate to 125 kHz. Logic Interface The SP9500 is designed to be compatible with TTL and CMOS logic levels. However, driving the digital inputs with TTL level signals will increase the power consumption of the part by 300 µA. In order to achieve the lowest power consumption use rail-to-rail CMOS levels to drive the digital inputs. +0.5 lsb DNLE -0.5 lsb +0.5 lsb INLE -0.5 lsb 0 CODE 4095 DNLE, INLE Plots |
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