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MAX11136 Datasheet(PDF) 11 Page - Maxim Integrated Products |
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MAX11136 Datasheet(HTML) 11 Page - Maxim Integrated Products |
11 / 40 page 11 MAX11135–MAX11143 500ksps, Low-Power, Serial 12-/10-/8-Bit, 4-/8-/16-Channel ADCs ELECTRICAL CHARACTERISTICS (MAX11141/MAX11142/MAX11143) (continued) (VDD = 2.35V to 3.6V, VOVDD = 1.5V to 3.6V, fSAMPLE = 500ksps, fSCLK = 8MHz, 50% duty cycle, VREF+ = VDD, TA = -40NC to +125NC, unless otherwise noted. Typical values are at TA = +25NC.) (Note 2) Note 2: Limits are 100% production tested at TA = +25NC. Limits over the operating temperature range are guaranteed by design. Note 3: Channel ID disabled. Note 4: Tested in single-ended mode. Note 5: Offset nulled. Note 6: Line rejection D(DOUT) with VDD = 2.35V to 3.6V and VREF+ = 2.35V. Note 7: Tested and guaranteed with fully differential input. Note 8: Conversion time is defined as the number of clock cycles multiplied by the clock period with a 50% duty cycle. Maximum conversion time: 4.73Fs + N x 16 x TOSC_MAX. Where N is the number of conversions requested (number of channels scanned, averaged and repeated). TOSC_MAX = 88.2ns, TOSC_TYP = 75ns. Note 9: The operational input voltage range for each individual input of a differentially configured pair is from VDD to GND. The operational input voltage difference is from -VREF+/2 to +VREF+/2 or -VREF+ to +VREF+. Note 10: See Figure 3 (Equivalent Input Circuit). Note 11: Guaranteed by characterization. PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS TIMING CHARACTERISTICS (Figure 1) (Note 11) SCLK Clock Period tCP Externally clocked conversion 125 ns SCLK Duty Cycle tCH 40 60 % SCLK Fall to DOUT Transition tDOT CLOAD = 10pF VOVDD = 1.5V to 2.35V 4 16.5 ns VOVDD = 2.35V to 3.6V 4 15 16th SCLK Fall to DOUT Disable tDOD CLOAD = 10pF, channel ID on 15 ns 14th SCLK Fall to DOUT Disable CLOAD = 10pF, channel ID off 16 ns SCLK Fall to DOUT Enable tDOE CLOAD = 10pF 14 ns DIN to SCLK Rise Setup tDS 4 ns SCLK Rise to DIN Hold tDH 1 ns CS Fall to SCLK Fall Setup tCSS 4 ns SCLK Fall to CS Fall Hold tCSH 1 ns CNVST Pulse Width tCSW See Figure 6 5 ns CS or CNVST Rise to EOC Low (Note 8) tCNV_INT See Figure 7, fSAMPLE = 500ksps 5.3 6.2 F s CS Pulse Width tCSBW 5 ns |
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