MCM69L736A

•MCM69L818A

6

MOTOROLA FAST SRAM

DC OPERATING CONDITIONS AND CHARACTERISTICS

(0

_C ≤ TA ≤ 70_C, Unless Otherwise Noted)

Parameter

Symbol

Min

Typical

–7.5

Typical

–8.5

Typical

–9.5

Typical

–10.5

Max

Unit

Notes

Input Reference DC Voltage

Vref (dc)

0.6

—

—

—

—

1.1

V

11

Core Power Supply Voltage

VDD

3.15

—

—

—

—

3.6

V

Output Driver Supply Voltage

VDDQ

1.4

—

—

—

—

1.6

V

Active Power Supply Current

(x18)

(x36)

IDD1

—

—

300

390

290

380

270

360

260

350

450

560

mA

5

Quiescent Active Power Supply Current)

IDD2

—

190

190

190

190

250

mA

6, 10

Active Standby Power Supply Current

ISB1

—

160

160

160

160

250

mA

7

Quiescent Standby Power Supply Current

ISB2

—

140

140

140

140

230

mA

8, 10

Sleep Mode Power Supply Current

ISB3

—

TBD

TBD

TBD

TBD

TBD

mA

9, 10

NOTES:

1. All data sheet parameters specified to full range of VDD unless otherwise noted. All voltages are referenced to voltage applied to VSS bumps.

2. Supply voltage applied to VDD connections.

3. Supply voltage applied to VDDQ connections.

4. All power supply currents measured with outputs open or deselected.

5. VDD = VDD (max), tKHKH = tKHKH (min), SS registered active, 50% read cycles.

6. VDD = VDD (max), tKHKH = dc, SS registered active.

7. VDD = VDD (max), tKHKH = tKHKH (min), SS registered inactive.

8. VDD = VDD (max), tKHKH = dc, SS registered inactive, ZZ low.

9. VDD = VDD (Max), tKHKH = dc, registered inactive, ZZ high.

10. 200 mV

≥ Vin ≥ VDDQ – 200 mV.

11. Although considerable latitude in the selection of the nominal dc value (i.e., rms value) of Vref is supported, the peak to peak ac component

superimposed on Vref may not exceed 5% of the dc component of Vref.

DC INPUT CHARACTERISTICS

Parameter

Symbol

Min

Max

Unit

Notes

DC Input Logic High

VIH (dc)

Vref + 0.1

VDD + 0.3

V

DC Input Logic Low

VIL (dc)

– 0.3

Vref – 0.1

V

1

Input Reference DC Voltage

Vref (dc)

0.6

1.1

V

2

Input Leakage Current

Ilkg(1)

—

± 5

µA

3

Clock Input Signal Voltage

Vin

– 0.3

VDD + 0.3

V

Clock Input Differential Voltage

VDIF (dc)

0.1

VDD + 0.6

V

4

Clock Input Common Mode Voltage Range (See Figure 3)

VCM (dc)

0.68

1.1

V

5

Clock Input Crossing Point Voltage Range

VX

0.68

1.1

V

NOTES:

1. Inputs may undershoot to – 0.5 V (peak) for up to 20% tKHKH (e.g., 2 ns at a clock cycle time of 10 ns).

2. Although considerable latitude in the selection of the nominal dc value (i.e., rms value) of Vref is supported, the peak–to–peak ac component

superimposed on Vref may not exceed 5% of the dc component of Vref.

3. 0 V

≤ Vin ≤ VDDQ for all pins.

4. Minimum instantaneous differential input voltage required for differential input clock operation.

5. Maximum rejectable common mode input voltage variation.