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CY7C006A-20AC Datasheet(PDF) 10 Page - Cypress Semiconductor |
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CY7C006A-20AC Datasheet(HTML) 10 Page - Cypress Semiconductor |
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10 / 22 page  CY7C006A/CY7C007A CY7C016A/CY7C017A Document Number: 38-06045 Rev. *F Page 10 of 22 Data Retention Mode The CY7C006A, CY7C007A, CY7C016A, and CY7C017A are designed with battery backup in mind. Data retention voltage and supply current are guaranteed over temperature. The following rules ensure data retention: 1. Chip Enable (CE) must be held HIGH during data retention, within VCC to VCC – 0.2 V. 2. CE must be kept between VCC – 0.2 V and 70% of VCC during the power-up and power-down transitions. 3. The RAM can begin operation >tRC after VCC reaches the minimum operating voltage (4.5 V). tBLC BUSY LOW from CE LOW 12 15 20 ns tBHC BUSY HIGH from CE HIGH 12 15 17 ns tPS Port Set-Up for Priority 5 5 5 ns tWB R/W HIGH after BUSY (Slave) 0 0 0 ns tWH R/W HIGH after BUSY HIGH (Slave) 11 13 15 ns tBDD[23] BUSY HIGH to Data Valid 12 15 20 ns INTERRUPT TIMING[24] tINS INT Set Time 12 15 20 ns tINR INT Reset Time 12 15 20 ns SEMAPHORE TIMING tSOP SEM Flag Update Pulse (OE or SEM)10 10 10 ns tSWRD SEM Flag Write to Read Time 5 5 5 ns tSPS SEM Flag Contention Window 5 5 5 ns tSAA SEM Address Access Time 12 15 20 ns Switching Characteristics Over the Operating Range[14] (continued) Parameter Description CY7C006A CY7C007A CY7C016A CY7C017A Unit –12[15] –15 –20 Min Max Min Max Min Max Timing Parameter Test Conditions[25] Max Unit ICCDR1 @ VCCDR = 2 V 1.5 mA Data Retention Mode 4.5V 4.5V VCC 2.0V VCC to VCC – 0.2V VCC CE tRC V IH Notes: 23. tBDD is a calculated parameter and is the greater of tWDD–tPWE (actual) or tDDD–tSD (actual). 24. Test conditions used are Load 2. 25. CE = VCC, Vin = GND to VCC, TA = 25C. This parameter is guaranteed but not tested. [+] Feedback |
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