CY7C131E, CY7C131AE

CY7C136E, CY7C136AE

1 K / 2 K × 8 Dual-port Static RAM

Cypress Semiconductor Corporation

•

198 Champion Court

•

San Jose

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408-943-2600

Document Number: 001-64231 Rev. *D

Revised June 15, 2012

1 K / 2 K × 8 Dual-port Static RAM

Features

reads of the same memory location

(CMOS) for optimum speed and power

both ports

plastic quad flat package (PQFP)

Functional Description

CY7C131E / CY7C131AE / CY7C136E / CY7C136AE are

high-speed, low-power CMOS 1 K / 2 K × 8 dual-port static

RAMs. Two ports are provided permitting independent access to

any location in memory. The CY7C131E / CY7C131AE /

CY7C136E / CY7C136AE can be used as a standalone dual-port

static RAM. It is the solution to applications requiring shared or

buffered data, such as cache memory for DSP, bit-slice, or multi-

processor designs.

Each port has independent control pins; chip enable (CE), write

enable (R/W), and output enable (OE). Two flags are provided

on each port, BUSY and INT. The BUSY flag signals that the port

is trying to access the same location, which is currently being

accessed by the other port. The INT is an interrupt flag indicating

that data is placed in a unique location[1]. The BUSY and INT

flags are push pull outputs. An automatic power-down feature is

controlled independently on each port by the chip enable (CE)

pins.

The CY7C131E / CY7C131AE / CY7C136E / CY7C136AE are

available in 52-pin Pb-free PLCC and 52-pin Pb-free PQFP.

ARBITRATION

LOGIC

(7C130/7C131 ONLY)

AND

INTERRUPT LOGIC

CONTROL

I/O

CONTROL

I/O

MEMORY

ARRAY

ADDR

DECODER

ADDR

DECODER

[2]

[3]

[3]

Logic Block Diagram

7C131E/7C131AE/

7C136E/7C136AE

ARBITRATION LOGIC

INTERRUPT LOGIC

[4]

[4]

[2]

Notes

1. Unique location used by interrupt flag: 1 K × 8: Left port reads from 3FE, Right port reads from 3FF; 2 K × 8: Left port reads from 7FE, Right port reads from 7FF.

2. BUSY is a push-pull output. No pull-up resistor required.

3. INT: push-pull output. No pull-up resistor required.

4. 1 K × 8: A0–A9, 2 K × 8: A0–A10, address lines are for both left and right ports.