CY7C130, CY7C130A

CY7C131, CY7C131A

Document Number: 38-06002 Rev. *H

Page 9 of 22

Switching Characteristics

Over the Operating Range[23, 24]

Parameter

Description

7C130-35

7C131-35

7C140-35

7C141-35

7C130-45

7C131-45

7C140-45

7C141-45

7C130-55

7C131-55

7C140-55

7C141-55

Unit

Min

Max

Min

Max

Min

Max

Read Cycle

Read cycle time

35

–

45

–

55

–

ns

Address to data valid[25]

–

35

–

45–55

ns

Data hold from address change

0

–

0

–

0

–

ns

CE LOW to data valid[25]

–

35

–

45–55

ns

–

20

–

25–25

ns

OE LOW to low Z[26, 27, 28]

3

–

3

–3–

ns

OE HIGH to high Z[26, 27, 28]

–

20

–

20–25

ns

CE LOW to low Z[26, 27, 28]

5

–

5

–5–

ns

CE HIGH to high Z[26, 27, 28]

–

20

–

20–25

ns

CE LOW to power-up[26]

0

–

0

–0–

ns

CE HIGH to power-down[26]

–

35

–

35–35

ns

Write Cycle[29]

Write cycle time

35

–

45

–

55

–

ns

CE LOW to write end

30

–

35

–

40

–

ns

Address set-up to write end

30

–

35

–

40

–

ns

Address hold from write end

2

–

2

–

2

–

ns

Address set-up to write start

0

–

0

–

0

–

ns

R/W pulse width

25

–

30

–

30

–

ns

Data set-up to write end

15

–

20

–

20

–

ns

Data hold from write end

0

–

0

–

0

–

ns

R/W LOW to high Z[28]

–

20

–

20–25

ns

R/W HIGH to low Z[28]

0

–

0

–0–

ns

Notes

23. See the last page of this specification for Group A subgroup testing information.

24. Test conditions assume signal transition times of 5 ns or less, timing reference levels of 1.5 V, input pulse levels of 0 to 3.0 V and output loading of the specified

26. This parameter is guaranteed but not tested.

29. The internal write time of the memory is defined by the overlap of CS LOW and R/W LOW. Both signals must be low to initiate a write and either signal can

terminate a write by going high. The data input setup and hold timing should be referenced to the rising edge of the signal that terminates the write.