CY7C131E, CY7C131AE

CY7C136E, CY7C136AE

Document Number: 001-64231 Rev. *D

Page 10 of 19

Switching Waveforms

Figure 4. Read Cycle No. 1 [28, 29]

Figure 5. Read Cycle No. 2 [28, 30]

Figure 6. Write Cycle No. 1 (OE Three-States Data I/Os – Either Port) [31, 32]

DATA VALID

PREVIOUS DATAVALID

DATA OUT

ADDR

Either Port ADDR Access

DATA VALID

DATA OUT

CE

OE

Either Port CE/OE Access

DATA VALID

HIGH IMPEDANCE

CE

R/W

ADDR

OE

Either Port

Notes

28. R/W is HIGH for read cycle.

30. Address valid prior to or coincident with CE transition LOW.

31. The internal write time of the memory is defined by the overlap of CE LOW and R/W LOW. Both signals must be LOW to initiate a write and either signal can

terminate a write by going HIGH. The data input setup and hold timing must be referenced to the rising edge of the signal that terminates the write.