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CY7C028V-15AXI Datasheet(PDF) 11 Page - Cypress Semiconductor |
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CY7C028V-15AXI Datasheet(HTML) 11 Page - Cypress Semiconductor |
11 / 22 page CY7C027V/027AV/028V CY7C037AV/038V Document #: 38-06078 Rev. *E Page 11 of 22 Notes 28. R/W must be HIGH during all address transitions. 29. A write occurs during the overlap (tSCE or tPWE) of a LOW CE or SEM and a LOW UB or LB. 30. tHA is measured from the earlier of CE or R/W or (SEM or R/W) going HIGH at the end of write cycle. 31. If OE is LOW during a R/W controlled write cycle, the write pulse width must be the larger of tPWE or (tHZWE + tSD) to allow the I/O drivers to turn off and data to be placed on the bus for the required tSD. If OE is HIGH during an R/W controlled write cycle, this requirement does not apply and the write pulse can be as short as the specified tPWE. 32. To access RAM, CE = VIL, SEM = VIH. 33. To access upper byte, CE = VIL, UB = VIL, SEM = VIH. To access lower byte, CE = VIL, LB = VIL, SEM = VIH. 34. Transition is measured 500 mV from steady state with a 5 pF load (including scope and jig). This parameter is sampled and not 100% tested. 35. During this period, the I/O pins are in the output state, and input signals must not be applied. 36. If the CE or SEM LOW transition occurs simultaneously with or after the R/W LOW transition, the outputs remain in the high impedance state. Switching Waveforms(continued) tAW tWC tPWE tHD tSD tHA CE R/W OE DATA OUT DATA IN ADDRESS tHZOE tSA tHZWE tLZWE Figure 7. Write Cycle No. 1: R/W Controlled Timing[28, 29, 30, 31] [34] [34] [31] [32,33] NOTE 35 NOTE 35 tAW tWC tSCE tHD tSD tHA CE R/W DATA IN ADDRESS tSA Figure 8. Write Cycle No. 2: CE Controlled Timing[28, 29, 30, 36] [32,33] |
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