CY7C131E, CY7C131AE

CY7C136E, CY7C136AE

Document Number: 001-64231 Rev. *D

Page 6 of 19

Switching Characteristics

Over the Operating Range

Parameter [11]

Description

7C131E-15/7C131AE-15

7C131E-25/7C136E-25

Unit

Min

Max

Min

Max

Read Cycle

Read cycle time

15

–25–

ns

Address to data valid [12]

–

15–25

ns

Data hold from Address change

3

–3–

ns

–

15–25

ns

OE LOW to data valid [12]

–

10–15

ns

OE LOW to Low Z [13, 14, 15]

3

–3–

ns

OE HIGH to High Z [13, 14, 15]

–

10–15

ns

CE LOW to Low Z [13, 14, 15]

3

–5–

ns

CE HIGH to High Z [13, 14, 15]

–

10–15

ns

CE LOW to power-up [13]

0

–0–

ns

CE HIGH to power-down [13]

–

15–25

ns

Write Cycle [16]

Write cycle time

15

–25–

ns

CE LOW to write end

12

–20–

ns

Address setup to write end

12

–20–

ns

Address hold from write end

0

–0–

ns

Address setup to write start

0

–0–

ns

R/W pulse width

10

–12–

ns

Data setup to write end

10

–15–

ns

Data hold from write end

0

–0–

ns

[13]

R/W LOW to High Z [15]

–

10–15

ns

[13]

R/W HIGH to Low Z [15]

3

–3–

ns

Notes

and 30 pF load capacitance.

13. This parameter is guaranteed but not tested.

state voltage.

16. The internal write time of the memory is defined by the overlap of CE LOW and R/W LOW. Both signals must be low to initiate a write and either signal can terminate