Electronic Components Datasheet Search |
|
CY7C131-55NXI Datasheet(PDF) 1 Page - Cypress Semiconductor |
|
CY7C131-55NXI Datasheet(HTML) 1 Page - Cypress Semiconductor |
1 / 22 page CY7C130, CY7C130A CY7C131, CY7C131A 1 K × 8 Dual-Port Static RAM Cypress Semiconductor Corporation • 198 Champion Court • San Jose , CA 95134-1709 • 408-943-2600 Document Number: 38-06002 Rev. *H Revised October 12, 2011 1 K × 8 Dual-Port Static RAM Features ■ True dual-ported memory cells, which allow simultaneous reads of the same memory location ■ 1 K × 8 organization ■ 0.65 micron CMOS for optimum speed and power ■ High speed access: 15 ns ■ Low operating power: ICC = 110 mA (maximum) ■ Fully asynchronous operation ■ Automatic power-down ■ Master CY7C130/130A/CY7C131/131A easily expands data bus width to 16 or more bits using slave CY7C140/CY7C141 ■ BUSY output flag on CY7C130/130A/CY7C131/131A; BUSY input on CY7C140/CY7C141 ■ INT flag for port-to-port communication ■ Available in 48-pin DIP (CY7C130/130A/140), 52-pin PLCC, 52-pin TQFP ■ Pb-free packages available Functional Description The CY7C130/130A/CY7C131/131A/CY7C140[1] and CY7C141 are high speed CMOS 1 K by 8 dual-port static RAMs. Two ports are provided permitting independent access to any location in memory. The CY7C130/130A/CY7C131/131A can be used as either a standalone 8-bit dual-port static RAM or as a master dual-port RAM in conjunction with the CY7C140/CY7C141 slave dual-port device in systems requiring 16-bit or greater word widths. It is the solution to applications requiring shared or buffered data, such as cache memory for DSP, bit-slice, or multi- processor designs. Each port has independent control pins; chip enable (CE), write enable (R/W), and output enable (OE). Two flags are provided on each port, BUSY and INT. BUSY signals that the port is trying to access the same location currently being accessed by the other port. INT is an interrupt flag indicating that data is placed in a unique location (3FF for the left port and 3FE for the right port). An automatic power down feature is controlled independently on each port by the chip enable (CE) pins. The CY7C130/130A and CY7C140 are available in 48-pin DIP. The CY7C131/131A and CY7C141 are available in 52-pin PLCC, 52-pin Pb-free PLCC, 52-pin PQFP, and 52-pin Pb-free PQFP. R/WL BUSYL CEL OEL A 9L A 0L A 0R A 9R R/WR CER OER CER OER CEL OEL R/WL R/WR I/O7L I/O0L I/O7R I/O0R BUSYR INTL INTR ARBITRATION LOGIC (7C130/7C131 ONLY) AND INTERRUPT LOGIC CONTROL I/O CONTROL I/O MEMORY ARRAY ADDRESS DECODER ADDRESS DECODER [2] [3] [3] Logic Block Diagram Notes 1. CY7C130 and CY7C130A are functionally identical; CY7C131 and CY7C131A are functionally identical. 2. CY7C130/130A/CY7C131/131A (Master): BUSY is open drain output and requires pull-up resistor. CY7C140/CY7C141 (Slave): BUSY is input. 3. Open drain outputs: pull-up resistor required. |
Similar Part No. - CY7C131-55NXI |
|
Similar Description - CY7C131-55NXI |
|
|
Link URL |
Privacy Policy |
ALLDATASHEET.NET |
Does ALLDATASHEET help your business so far? [ DONATE ] |
About Alldatasheet | Advertisement | Contact us | Privacy Policy | Link Exchange | Manufacturer List All Rights Reserved©Alldatasheet.com |
Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
Family Site : ic2ic.com |
icmetro.com |