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CY7C136A-55JXI Datasheet(PDF) 5 Page - Cypress Semiconductor |
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CY7C136A-55JXI Datasheet(HTML) 5 Page - Cypress Semiconductor |
5 / 17 page CY7C132, CY7C136 CY7C136A, CY7C142, CY7C146 Document #: 38-06031 Rev. *H Page 5 of 17 Write Cycle[12] tWC Write Cycle Time 15 25 30 ns tSCE CE LOW to Write End 12 20 25 ns tAW Address Setup to Write End 12 20 25 ns tHA Address Hold from Write End 2 22 ns tSA Address Setup to Write Start 0 00 ns tPWE R/W Pulse Width 12 15 25 ns tSD Data Setup to Write End 10 15 15 ns tHD Data Hold from Write End 0 00 ns tHZWE R/W LOW to High Z [7] 10 15 15 ns tLZWE R/W HIGH to Low Z [7] 0 00 ns Busy/Interrupt Timing tBLA BUSY LOW from Address Match 15 20 20 ns tBHA BUSY HIGH from Address Mismatch[13] 15 20 20 ns tBLC BUSY LOW from CE LOW 15 20 20 ns tBHC BUSY HIGH from CE HIGH[13] 15 20 20 ns tPS Port Set Up for Priority 5 55 ns tWB R/W LOW after BUSY LOW[14] 0 00 ns tWH R/W HIGH after BUSY HIGH 13 20 30 ns tBDD BUSY HIGH to Valid Data 15 25 30 ns tDDD Write Data Valid to Read Data Valid Note 15 Note 15 Note 15 ns tWDD Write Pulse to Data Delay Note 15 Note 15 Note 15 ns Interrupt Timing [16] tWINS R/W to INTERRUPT Set Time 15 25 25 ns tEINS CE to INTERRUPT Set Time 15 25 25 ns tINS Address to INTERRUPT Set Time 15 25 25 ns tOINR OE to INTERRUPT Reset Time[13] 15 25 25 ns tEINR CE to INTERRUPT Reset Time[13] 15 25 25 ns tINR Address to INTERRUPT Reset Time[13] 15 25 25 ns Shaded areas contain preliminary information. Switching Characteristics Over the Operating Range (Speeds -15, -25, -30) [8] (continued) Parameter Description 7C136-15 [4] 7C146-15 7C132-25 [4] 7C136-25 7C142-25 7C146-25 7C132-30 7C136-30 7C142-30 7C146-30 Unit Min Max Min Max Min Max Notes 12. The internal write time of the memory is defined by the overlap of CE LOW and R/W LOW. Both signals must be LOW to initiate a write and either signal can terminate a write by going HIGH. The data input setup and hold timing must be referenced to the rising edge of the signal that terminates the write. 13. These parameters are measured from the input signal changing, until the output pin goes to a high impedance state. 14. CY7C142/CY7C146 only. 15. A write operation on Port A, where Port A has priority, leaves the data on Port B’s outputs undisturbed until one access time after one of the following: BUSY on Port B goes HIGH. Port B’s address toggled. CE for Port B is toggled. R/W for Port B is toggled during valid read. 16. 52-pin PLCC and PQFP versions only. |
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