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CY7C421-20JXC Datasheet(PDF) 1 Page - Cypress Semiconductor |
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CY7C421-20JXC Datasheet(HTML) 1 Page - Cypress Semiconductor |
1 / 21 page CY7C421 512 × 9 Asynchronous FIFO Cypress Semiconductor Corporation • 198 Champion Court • San Jose , CA 95134-1709 • 408-943-2600 Document Number: 38-06001 Rev. *H Revised August 7, 2012 512 × 9 Asynchronous FIFO Features ■ Asynchronous First-In First-Out (FIFO) Buffer Memories ❐ 512 × 9 (CY7C421) ■ Dual-Ported RAM Cell ■ High Speed 50 MHz Read and Write Independent of Depth and Width ■ Low Operating Power: ICC = 35 mA ■ Empty and Full Flags (Half Full Flag in Standalone) ■ TTL Compatible ■ Retransmit in Standalone ■ Expandable in Width ■ PLCC, 7 × 7 TQFP, 300-Mil Molded SOJ ■ Pb-free Packages Available ■ Pin Compatible and Functionally Equivalent to IDT7201, and AM7201 Functional Description The CY7C421 is a first-in first-out (FIFO) memory offered in 300-mil wide SOJ, TQFP & PLCC packages and it is 512 words by 9 bits wide. Each FIFO memory is organized such that the data is read in the same sequential order that it was written. Full and empty flags are provided to prevent overflow and underflow. Three additional pins are also provided to facilitate unlimited expansion in width, depth, or both. The depth expansion technique steers the control signals from one device to another in parallel. This eliminates the serial addition of propagation delays, so that throughput is not reduced. Data is steered in a similar manner. The read and write operations may be asynchronous; each can occur at a rate of 50 MHz. The write operation occurs when the write (W) signal is LOW. Read occurs when read (R) goes LOW. The nine data outputs go to the high impedance state when R is HIGH. A Half Full (HF) output flag that is valid in the standalone and width expansion configurations is provided. In the depth expansion configuration, this pin provides the expansion out (XO) information that is used to tell the next FIFO that it is activated. In the standalone and width expansion configurations, a LOW on the retransmit (RT) input causes the FIFO to retransmit the data. Read enable (R) and write enable (W) must both be HIGH during retransmit, and then R is used to access the data. The CY7C421 is fabricated using an advanced 0.65-micron P-well CMOS technology. Input ESD protection is greater than 2000 V and latch up is prevented by careful layout and guard rings. Selection Guide 512 × 9 -15 -20 Frequency (MHz) 40 33.3 Maximum Access Time (ns) 15 20 ICC1 (mA) 35 35 CY7C421512 × 9 Asynchronous FIFO |
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