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CY7C028V-25AXC Datasheet(PDF) 1 Page - Cypress Semiconductor |
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CY7C028V-25AXC Datasheet(HTML) 1 Page - Cypress Semiconductor |
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1 / 22 page  CY7C027V/027AV/028V CY7C037AV/038V 3.3 V 32K/64K x 16/18 Dual-Port Static RAM Cypress Semiconductor Corporation • 198 Champion Court • San Jose , CA 95134-1709 • 408-943-2600 Document #: 38-06078 Rev. *E Revised October 14, 2011 Features ■ True dual-ported memory cells which allow simultaneous access of the same memory location ■ 32K x 16 organization (CY7C027V/027AV [1]) ■ 64K x 16 organization (CY7C028V) ■ 32K x 18 organization (CY7C037AV) ■ 64K x 18 organization (CY7C038V) ■ 0.35 micron Complementary metal oxide semiconductor (CMOS) for optimum speed and power ■ High speed access: 15, 20, and 25 ns ■ Low operating power ■ Active: ICC = 115 mA (typical) ■ Standby: ISB3 = 10 A (typical) ■ Fully asynchronous operation ■ Automatic power-down ■ Expandable data bus to 32/36 bits or more using Master/Slave chip select when using more than one device ■ On-chip arbitration logic ■ Semaphores included to permit software handshaking between ports ■ INT flag for port-to-port communication ■ Separate upper-byte and lower-byte control ■ Dual chip enables ■ Pin select for Master or Slave ■ Commercial and Industrial temperature ranges ■ 100-pin Pb-free Thin quad plastic flatpack (TQFP) and 100-pin TQFP Notes 1. CY7C027V, and CY7C027AV are functionally identical. 2. I/O8–I/O15 for x16 devices; I/O9–I/O17 for x18 devices. 3. I/O0–I/O7 for x16 devices; I/O0–I/O8 for x18 devices. 4. A0–A14 for 32K; A0–A15 for 64K devices. 5. BUSY is an output in master mode and an input in slave mode. R/WL CE0L CE1L OEL I/O8/9L–I/O15/17L I/O Control Address Decode A0L–A14/15L CEL OEL R/WL BUSYL I/O Control CEL Interrupt Semaphore Arbitration SEML INTL M/S UBL LBL I/O0L–I/O7/8L R/WR CE0R CE1R OER I/O8/9L–I/O15/17R CER UBR LBR I/O0L–I/O7/8R UBL LBL Logic Block Diagram A0L–A14/15L True Dual-Ported RAM Array A0R–A14/15R CER OER R/WR BUSYR SEMR INTR UBR LBR Address Decode A0R–A14/15R [2] [2] [3] [3] [4] [4] [5] [5] [4] [4] 15/16 8/9 8/9 15/16 8/9 8/9 15/16 15/16 |
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