CY7C0831AV, CY7C0832AV

CY7C0832BV, CY7C0833V

Document #: 38-06059 Rev. *W

Page 8 of 31

Counter Reset Operation

All unmasked bits of the counter are reset to ‘0.’ All masked bits

remain unchanged. The mirror register is loaded with the value

of the burst counter. A Mask Reset followed by a Counter Reset

resets the counter and mirror registers to 00000, as does master

reset (MRST).

Counter Load Operation

The address counter and mirror registers are both loaded with

the address value presented at the address lines.

Counter Increment Operation

When the address counter register is initially loaded with an

external address, the counter can internally increment the

address value, potentially addressing the entire memory array.

Only the unmasked bits of the counter register are incremented.

The corresponding bit in the mask register must be a ‘1’ for a

counter bit to change. The counter register is incremented by 1

if the least significant bit is unmasked, and by 2 if it is masked. If

all unmasked bits are ‘1,’ the next increment wraps the counter

back to the initially loaded value. If an Increment results in all the

unmasked bits of the counter being ‘1s,’ a counter interrupt flag

(CNTINT) is asserted. The next Increment returns the counter

register to its initial value, which was stored in the mirror register.

The counter address can instead be forced to loop to 00000 by

externally connecting CNTINT to CNTRST.[18] An increment that

results in one or more of the unmasked bits of the counter being

‘0’ deasserts the counter interrupt flag. The example in Figure 4

on page 11 shows the counter mask register loaded with a mask

value of 0003Fh unmasking the first 6 bits with bit ‘0’ as the LSB

and bit ‘16’ as the MSB. The maximum value the mask register

can be loaded with is 3FFFFh. Setting the mask register to this

value allows the counter to access the entire memory space. The

address counter is then loaded with an initial value of 8h. The

base address bits (in this case, the 6th address through the 16th

address) are loaded with an address value but do not increment

after the counter is configured for increment operation. The

counter address starts at address 8h. The counter increments its

internal address value until it reaches the mask register value of

3Fh. The counter wraps around the memory block to location 8h

at the next count. CNTINT is issued when the counter reaches

its maximum value

Counter Hold Operation

The value of all three registers can be constantly maintained

unchanged for an unlimited number of clock cycles. Such

operation is useful in applications where wait states are needed,

or when address is available a few cycles ahead of data in a

shared bus interface.

Counter Interrupt

The counter interrupt (CNTINT) is asserted LOW when an

increment operation results in the unmasked portion of the

counter register being all ‘1s.’ It is deasserted HIGH when an

Increment operation results in any other value. It is also

de-asserted by Counter Reset, Counter Load, Mask Reset and

Mask Load operations, and by MRST.

Counter Readback Operation

The internal value of the counter register can be read out on the

after the next rising edge of the port’s clock. If address readback

occurs while the port is enabled (CE0 LOW and CE1 HIGH), the

data lines (DQs) are three-stated. Figure 3 on page 10 shows a

block diagram of the operation.

Table 1. Interrupt Operation Example [12, 13, 14, 15, 16, 17]

Function

Left Port

Right Port

L

L

3FFFF

XXXX

L

XXXX

H

L

3FFFF

H

XXX

L

L

L

3FFFE

X

H

L

3FFFE

H

XXXX

L

L

3FFFF

XXXX

L

Notes

12. CY7C0831AV has 17 address bits, CY7C0832AV/CY7C0832BV has 18 address bits and CY7C0833V has 19 address bits.

can be deasserted after that. Data is out after the following CLK edge and is three-stated after the next CLK edge.

14. OE is “Don’t Care” for mailbox operation.

15. At least one of BE0, BE1 must be LOW.

16. A18x is a NC for CY7C0832AV/CY7C0832BV, therefore the Interrupt Addresses are 3FFFF and 3FFFE. A18x and A17x are NC for CY7C0831AV, therefore the

Interrupt addresses are 1FFFF and 1FFFE.

17. “X” = “Don’t Care,” “H” = HIGH, “L” = LOW.

18. CNTINT and CNTRST specs are guaranteed by design to operate properly at speed grade operating frequency when tied together.