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CY7C136E-55NXC Datasheet(PDF) 8 Page - Cypress Semiconductor |
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CY7C136E-55NXC Datasheet(HTML) 8 Page - Cypress Semiconductor |
8 / 19 page CY7C131E, CY7C131AE CY7C136E, CY7C136AE Document Number: 001-64231 Rev. *D Page 8 of 19 Switching Characteristics Over the Operating Range Parameter Description 7C131E-55 7C136E-55 7C136AE-55 Unit Min Max Read Cycle tRC Read cycle time 55 – ns tAA Address to data valid [21] –55 ns tOHA Data hold from Address change 3 – ns tACE CE LOW to data valid [21] –55 ns tDOE OE LOW to data valid [21] –25 ns tLZOE OE LOW to Low Z [21, 22, 23] 3– ns tHZOE OE HIGH to High Z [21, 22, 23] –25 ns tLZCE CE LOW to Low Z [21, 22, 23] 5– ns tHZCE CE HIGH to High Z [21, 22, 23] –25 ns tPU CE LOW to power-up [22] 0– ns tPD CE HIGH to power-down [22] –35 ns Write Cycle tWC Write cycle time 55 – ns tSCE CE LOW to write end 40 – ns tAW Address setup to write end 40 – ns tHA Address hold from write end 2 – ns tSA Address setup to write start 0 – ns tPWE R/W pulse width 30 – ns tSD Data setup to write end 20 – ns tHD Data hold from write end 0 – ns tHZWE R/W LOW to High Z [24] –25 ns tLZWE R/W HIGH to Low Z [24] 3– ns Busy/Interrupt Timing[20] tBLA BUSY LOW from Address match – 30 ns tBHA BUSY HIGH from Address mismatch [25] –30 ns tBLC BUSY LOW from CE LOW – 30 ns tBHC BUSY HIGH from CE HIGH [25] –30 ns tPS Port setup for priority 5 – ns tBDD BUSY HIGH to valid data – 45 ns Notes 20. Test conditions used are Load 2. 21. The internal write time of the memory is defined by the overlap of CE LOW and R/W LOW. Both signals must be low to initiate a write and either signal can terminate a write by going high. The data input setup and hold timing should be referenced to the rising edge of the signal that terminates the write. 22. AC Test Conditions use VOH = 1.6 V and VOL = 1.4 V. 23. These parameters are measured from the input signal changing, until the output pin goes to a high impedance state. 24. Parameters tLZCE, tLZWE, tHZOE, tLZOE, tHZCE and tHZWE are tested with C = 5 pF as in part (b) of Figure 3 on page 5. Transition is measured ±500 mV from steady state voltage. 25. A write operation on Port A, where Port A has priority, leaves the data on Port B’s outputs undisturbed until one access time after one of the following: BUSY on Port B goes HIGH. Port B’s address toggled. |
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