CY7C1019CV33

Document #: 38-05130 Rev. *K

Page 7 of 13

Switching Waveforms

Figure 3. Read Cycle No. 1 [11, 12]

Figure 4. Read Cycle No. 2 (OE Controlled) [12, 13]

Figure 5. Write Cycle No. 1 (CE Controlled) [14, 15]

PREVIOUS DATA VALID

DATA VALID

ADDRESS

DATA OUT

50%

50%

DATA VALID

HIGH IMPEDANCE

HIGH

OE

CE

ICC

ISB

IMPEDANCE

ADDRESS

DATA OUT

SUPPLY

CURRENT

DATA VALID

CE

ADDRESS

WE

DATA I/O

Notes

12. WE is HIGH for read cycle.

13. Address valid prior to or coincident with CE transition LOW.

15. If CE goes HIGH simultaneously with WE going HIGH, the output remains in a high impedance state.

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