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CY7C0852V-133BBC Datasheet(PDF) 7 Page - Cypress Semiconductor |
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CY7C0852V-133BBC Datasheet(HTML) 7 Page - Cypress Semiconductor |
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7 / 39 page  CY7C0851V/CY7C0851AV CY7C0852V/CY7C0852AV CY7C0853V/CY7C0853AV Document Number: 38-06070 Rev. *L Page 7 of 39 Pin Definitions Left Port Right Port Description A0L–A17L [3] A0R–A17R [3] Address inputs. ADSL [4] ADSR [4] Address strobe input. Used as an address qualifier. This signal should be asserted LOW for the part using the externally supplied address on the address pins and for loading this address into the burst address counter. CE0L [4] CE0R [4] Active LOW chip enable input. CE1L [4] CE1R [4] Active HIGH chip enable input. CLKL CLKR Clock signal. Maximum clock input rate is fMAX. CNTENL [4] CNTENR [4] Counter enable input. Asserting this signal LOW increments the burst address counter of its respective port on each rising edge of CLK. The increment is disabled if ADS or CNTRST are asserted LOW. CNTRSTL [4] CNTRSTR [4] Counter reset input. Asserting this signal LOW resets to zero the unmasked portion of the burst address counter of its respective port. CNTRST is not disabled by asserting ADS or CNTEN. CNT/MSKL [4] CNT/MSKR [4] Address counter mask register enable input. Asserting this signal LOW enables access to the mask register. When tied HIGH, the mask register is not accessible and the address counter operations are enabled based on the status of the counter control signals. DQ0L–DQ35L DQ0R–DQ35R Data bus input/output. OEL OER Output enable input. This asynchronous signal must be asserted LOW to enable the DQ data pins during Read operations. INTL INTR Mailbox interrupt flag output. The mailbox permits communications between ports. The upper two memory locations can be used for message passing. INTL is asserted LOW when the right port writes to the mailbox location of the left port, and vice versa. An interrupt to a port is deasserted HIGH when it reads the contents of its mailbox. CNTINTL [4] CNTINTR [4] Counter interrupt output. This pin is asserted LOW when the unmasked portion of the counter is incremented to all “1s.” R/WL R/WR Read/Write enable input. Assert this pin LOW to write to, or HIGH to Read from the dual port memory array. B0L–B3L B0R–B3R Byte select inputs. Asserting these signals enables Read and Write operations to the corresponding bytes of the memory array. MRST Master reset input. MRST is an asynchronous input signal and affects both ports. Asserting MRST LOW performs all of the reset functions as described in the text. A MRST operation is required at power up. TMS JTAG test mode select input. It controls the advance of JTAG TAP state machine. State machine transitions occur on the rising edge of TCK. TDI JTAG test data input. Data on the TDI input is shifted serially into selected registers. TCK JTAG test clock input. TDO JTAG test data output. TDO transitions occur on the falling edge of TCK. TDO is normally three-stated except when captured data is shifted out of the JTAG TAP. VSS Ground inputs. VDD Power inputs. Notes 3. 9M device has 18 address bits, 4M device has 17 address bits, and 2M device has 16 address bits. 4. These pins are not available for CY7C0853V/CY7C0853AV device. |
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