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CY7C2563XV18 Datasheet(PDF) 9 Page - Cypress Semiconductor |
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CY7C2563XV18 Datasheet(HTML) 9 Page - Cypress Semiconductor |
9 / 29 page CY7C2563XV18, CY7C2565XV18 Document Number: 001-68997 Rev. *B Page 9 of 29 Truth Table The truth table for CY7C2563XV18, and CY7C2565XV18 follows. [3, 4, 5, 6, 7, 8, 9, 10] Operation K RPS WPS DQ DQ DQ DQ Write Cycle: Load address on the rising edge of K; input write data on two consecutive K and K rising edges. L–H H [9] L [10] D(A) at K(t + 1) D(A + 1) at K(t + 1) D(A + 2) at K(t + 2) D(A + 3) at K(t + 2) Read Cycle: (2.5 cycle Latency) Load address on the rising edge of K; wait two and half cycles; read data on two consecutive K and K rising edges. L–H L [10] X Q(A) at K(t + 2) Q(A + 1) at K(t + 3) Q(A + 2) at K(t + 3) Q(A + 3) at K(t + 4) NOP: No Operation L–H H H D = X Q = High Z D = X Q = High Z D = X Q = High Z D = X Q = High Z Standby: Clock Stopped Stopped X X Previous State Previous State Previous State Previous State Write Cycle Descriptions The write cycle description table for CY7C2563XV18 follows. [3, 11] BWS0 BWS1 K K Comments L L L–H – During the data portion of a write sequence: CY7C2563XV18 both bytes (D [17:0]) are written into the device. L L – L–H During the data portion of a write sequence: CY7C2563XV18 both bytes (D [17:0]) are written into the device. L H L–H – During the data portion of a write sequence: CY7C2563XV18 only the lower byte (D [8:0]) is written into the device, D[17:9] remains unaltered. L H – L–H During the data portion of a write sequence: CY7C2563XV18 only the lower byte (D [8:0]) is written into the device, D[17:9] remains unaltered. H L L–H – During the data portion of a write sequence: CY7C2563XV18 only the upper byte (D [17:9]) is written into the device, D[8:0] remains unaltered. H L – L–H During the data portion of a write sequence: CY7C2563XV18 only the upper byte (D [17:9]) is written into the device, D[8:0] remains unaltered. H H L–H – No data is written into the devices during this portion of a write operation. H H – L–H No data is written into the devices during this portion of a write operation. Notes 3. X = “Don't Care,” H = Logic HIGH, L = Logic LOW, represents rising edge. 4. Device powers up deselected with the outputs in a tri-state condition. 5. “A” represents address location latched by the devices when transaction was initiated. A + 1, A + 2, and A + 3 represents the address sequence in the burst. 6. “t” represents the cycle at which a read/write operation is started. t + 1, t + 2, and t + 3 are the first, second and third clock cycles respectively succeeding the “t” clock cycle. 7. Data inputs are registered at K and K rising edges. Data outputs are delivered on K and K rising edges as well. 8. Ensure that when clock is stopped K = K and C = C = HIGH. This is not essential, but permits most rapid restart by overcoming transmission line charging symmetrically. 9. If this signal was LOW to initiate the previous cycle, this signal becomes a “Don’t Care” for this operation. 10. This signal was HIGH on previous K clock rise. Initiating consecutive read or write operations on consecutive K clock rises is not permitted. The device ignores the second read or write request. 11. Is based on a write cycle that was initiated in accordance with the Truth Table on page 9. BWS0, BWS1, BWS2, and BWS3 can be altered on different portions of a write cycle, as long as the setup and hold requirements are achieved. |
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