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CY7C2568XV18 Datasheet(PDF) 3 Page - Cypress Semiconductor

Part # CY7C2568XV18
Description  72-Mbit DDR II Xtreme SRAM Two-Word Burst Architecture (2.5 Cycle Read Latency) with ODT
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Manufacturer  CYPRESS [Cypress Semiconductor]
Direct Link  http://www.cypress.com
Logo CYPRESS - Cypress Semiconductor

CY7C2568XV18 Datasheet(HTML) 3 Page - Cypress Semiconductor

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CY7C2568XV18, CY7C2570XV18
Document Number: 001-70206 Rev. *B
Page 3 of 29
Contents
Pin Configurations ........................................................... 4
Pin Definitions .................................................................. 5
Functional Overview ........................................................ 7
Read Operations ......................................................... 7
Write Operations ......................................................... 7
Byte Write Operations ................................................. 7
DDR Operation ............................................................ 7
Depth Expansion ......................................................... 7
Programmable Impedance .......................................... 7
Echo Clocks ................................................................ 7
Valid Data Indicator (QVLD) ........................................ 8
On-Die Termination (ODT) .......................................... 8
PLL .............................................................................. 8
Application Example ........................................................ 8
Truth Table ........................................................................ 9
Write Cycle Descriptions ................................................. 9
Write Cycle Descriptions ............................................... 10
IEEE 1149.1 Serial Boundary Scan (JTAG) .................. 11
Disabling the JTAG Feature ...................................... 11
Test Access Port ....................................................... 11
Performing a TAP Reset ........................................... 11
TAP Registers ........................................................... 11
TAP Instruction Set ................................................... 11
TAP Controller State Diagram ....................................... 13
TAP Controller Block Diagram ...................................... 14
TAP Electrical Characteristics ...................................... 14
TAP AC Switching Characteristics ............................... 15
TAP Timing and Test Conditions .................................. 16
Identification Register Definitions ................................ 17
Scan Register Sizes ....................................................... 17
Instruction Codes ........................................................... 17
Boundary Scan Order .................................................... 18
Power Up Sequence in DDR II+ Xtreme SRAM ............ 19
Power Up Sequence ................................................. 19
PLL Constraints ......................................................... 19
Maximum Ratings ........................................................... 20
Operating Range ............................................................. 20
Neutron Soft Error Immunity ......................................... 20
Electrical Characteristics ............................................... 20
DC Electrical Characteristics ..................................... 20
AC Electrical Characteristics ..................................... 21
Capacitance .................................................................... 22
Thermal Resistance ........................................................ 22
AC Test Loads and Waveforms ..................................... 22
Switching Characteristics .............................................. 23
Switching Waveforms .................................................... 24
Read/Write/Deselect Sequence ................................ 24
Ordering Information ...................................................... 25
Ordering Code Definitions ......................................... 25
Package Diagram ............................................................ 26
Acronyms ........................................................................ 27
Document Conventions ................................................. 27
Units of Measure ....................................................... 27
Document History Page ................................................. 28
Sales, Solutions, and Legal Information ...................... 29
Worldwide Sales and Design Support ....................... 29
Products .................................................................... 29
PSoC Solutions ......................................................... 29


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