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CY7C2562XV18-366BZXC Datasheet(PDF) 8 Page - Cypress Semiconductor |
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CY7C2562XV18-366BZXC Datasheet(HTML) 8 Page - Cypress Semiconductor |
8 / 27 page CY7C2562XV18, CY7C2564XV18 Document Number: 001-70204 Rev. *B Page 8 of 27 Echo Clocks Echo clocks are provided on the QDR II+ to simplify data capture on high-speed systems. Two echo clocks are generated by the QDR II+. CQ is referenced with respect to K and CQ is referenced with respect to K. These are free running clocks and are synchronized to the input clock of the QDR II+. The timing for echo clocks is shown in Switching Characteristics on page 22. Valid Data Indicator (QVLD) QVLD is provided on the QDR II+ to simplify data capture on high speed systems. The QVLD is generated by the QDR II+ device along with data output. This signal is also edge-aligned with the echo clock and follows the timing of any data pin. This signal is asserted half a cycle before valid data arrives. On-Die Termination (ODT) These devices have an On-Die Termination feature for Data inputs (D[x:0]), Byte Write Selects (BWS[x:0]), and Input Clocks (K and K). The termination resistors are integrated within the chip. The ODT range selection is enabled through ball R6 (ODT pin). The ODT termination tracks value of RQ where RQ is the resistor tied to the ZQ pin. ODT range selection is made during power-up initialization. A LOW on this pin selects a low range that follows RQ/3.33 for 175 < RQ < 350 (where RQ is the resistor tied to ZQ pin) A HIGH on this pin selects a high range that follows RQ/1.66 for 175 < RQ < 250 (where RQ is the resistor tied to ZQ pin). When left floating, a high range termination value is selected by default. For a detailed description on the ODT implementation, refer to the application note, On-Die Termination for QDRII+/DDRII+ SRAMs. PLL These chips use a PLL that is designed to function between 120 MHz and the specified maximum clock frequency. During power up, when the DOFF is tied HIGH, the PLL is locked after 100 s of stable clock. The PLL can also be reset by slowing or stopping the input clocks K and K for a minimum of 30 ns. However, it is not necessary to reset the PLL to lock to the desired frequency. The PLL automatically locks 100 s after a stable clock is presented. The PLL may be disabled by applying ground to the DOFF pin. When the PLL is turned off, the device behaves in QDR I mode with one cycle latency and a longer access time). For information, refer to the application note, PLL Considerations in QDRII/DDRII/QDRII+/DDRII+. Application Example Figure 2 shows two QDR II+ used in an application. Figure 2. Application Example BUS MASTER (CPU or ASIC) DATA IN DATA OUT Address Source K Source K Vt Vt Vt R R D A K SRAM #2 RQ = 250 ohms ZQ CQ/CQ Q K RPS WPS BWS D A K SRAM #1 RQ = 250 ohms ZQ CQ/CQ Q K RPS WPS BWS RPS WPS BWS CLKIN1/CLKIN1 R = 50ohms, Vt = V /2 DDQ R ODT ODT ODT R CLKIN2/CLKIN2 |
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