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CY8C20424-12LQXI Datasheet(PDF) 10 Page - Cypress Semiconductor |
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CY8C20424-12LQXI Datasheet(HTML) 10 Page - Cypress Semiconductor |
10 / 41 page CY8C20224, CY8C20324 CY8C20424, CY8C20524 Document Number: 001-41947 Rev. *L Page 10 of 41 32-pin Part Pinout Figure 6. CY8C20424 32-pin PSoC Device A I, P 0 [1 ] AI, P2 [7 ] AI, P2 [5 ] AI, P2 [3 ] AI, P2 [1 ] AI, P3 [3 ] QF N (T o p V ie w ) 1 2 3 4 5 6 7 8 24 23 22 21 20 19 18 17 A I, P 3 [1 ] SPI SS , P1 [7 ] P0 [0 ], AI P2 [6 ], AI P3 [0 ], AI XR ES P2 [4 ], AI P2 [2 ], AI P2 [0 ], AI P3 [2 ], AI A I, I2 C S C L Notes 5. The center pad on the QFN package is connected to ground (VSS) for best mechanical, thermal, and electrical performance. If not connected to ground, it is electrically floated and not connected to any other signal. 6. These are the ISSP pins, that are not high Z at POR (Power on reset). Refer the PSoC Programmable System-on-Chip Technical Reference Manual for details. Table 4. 32-pin Part Pinout (QFN [5]) Pin No. Digital Analog Name Description 1 I/O I P0[1] Integrating Input 2 I/O IP2[7] 3 I/O IP2[5] 4 I/O I P2[3] 5 I/O I P2[1] 6 I/O IP3[3] 7 I/O I P3[1] 8 IOH I P1[7] I2C SCL, SPI SS 9 IOH I P1[5] I2C SDA, SPI MISO 10 IOH I P1[3] SPI CLK 11 IOH I P1[1] CLK[6], I2C SCL, SPI MOSI 12 Power VSS Ground connection 13 IOH I P1[0] DATA[6], I2C SDA 14 IOH I P1[2] 15 IOH I P1[4] Optional external clock input (EXTCLK) 16 IOH I P1[6] 17 Input XRES Active high external reset with internal pull-down 18 I/O IP3[0] 19 I/O IP3[2] 20 I/O IP2[0] 21 I/O I P2[2] |
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