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CY14B256LA-SP45XI Datasheet(PDF) 4 Page - Cypress Semiconductor |
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CY14B256LA-SP45XI Datasheet(HTML) 4 Page - Cypress Semiconductor |
4 / 22 page CY14B256LA Document Number: 001-54707 Rev. *I Page 4 of 22 Pin Definitions Pin Name I/O Type Description A0–A14 Input Address inputs. Used to select one of the 32,768 bytes of the nvSRAM. DQ0–DQ7 Input/Output Bidirectional data I/O lines. Used as input or output lines depending on operation. WE Input Write enable input, active LOW. When the chip is enabled and WE is LOW, data on the I/O pins is written to the specific address location. CE Input Chip enable input, active LOW. When LOW, selects the chip. When HIGH, deselects the chip. OE Input Output enable, active LOW. The active LOW OE input enables the data output buffers during read cycles. I/O pins are tristated on deasserting OE HIGH. VSS Ground Ground for the device. Must be connected to the ground of the system. VCC Power supply Power supply inputs to the device. 3.0 V +20%, –10% HSB Input/Output Hardware STORE busy (HSB). When LOW this output indicates that a Hardware STORE is in progress. When pulled LOW external to the chip it initiates a nonvolatile STORE operation. After each Hardware and Software STORE operation HSB is driven HIGH for a short time (tHHHD) with standard output high current and then a weak internal pull-up resistor keeps this pin HIGH (External pull-up resistor connection optional). VCAP Power supply AutoStore capacitor. Supplies power to the nvSRAM during power loss to store data from SRAM to nonvolatile elements. NC No connect No connect. This pin is not connected to the die. |
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