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CY22801KFXCT Datasheet(PDF) 9 Page - Cypress Semiconductor |
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CY22801KFXCT Datasheet(HTML) 9 Page - Cypress Semiconductor |
9 / 25 page CY22801 Document Number: 001-15571 Rev. *H Page 9 of 25 PLL Frequency, P Counter [40H(1..0)], [41H(7..0)], [42H(7)] The next counter definition is the P (product) counter. The P counter is multiplied with the (REF/Qtotal) value to achieve the VCO frequency. The product counter, defined as Ptotal, is made up of two internal variables, PB and PO. The formula for calculating Ptotal is: Ptotal = (2(PB + 4) + PO) PB is a 10-bit variable, defined by registers 40H(1:0) and 41H(7:0). The 2 LSBs of register 40H are the two MSBs of variable PB. Bits 4..2 of register 40H are used to determine the charge pump settings. The three MSBs of register 40H are preset and reserved and cannot be changed. PO is a single bit variable, defined in register 42H(7). This allows for odd numbers in Ptotal. The remaining seven bits of 42H are used to define the Q counter, as shown in Table 8. The minimum value of Ptotal is 8. The maximum value of Ptotal is 2055. To achieve the minimum value of Ptotal, PB and PO should both be programmed to 0. To achieve the maximum value of Ptotal, PB should be programmed to 1023, and PO should be programmed to 1. Stable operation of the CY22801 cannot be guaranteed if the value of (Ptotal × (REF/Qtotal)) is above 400 MHz or below 100 MHz. PLL Post Divider Options [0CH(7..0)], [47H(7..0)] The output of the VCO is routed through two independent muxes, then to two divider banks to determine the final clock output frequency. The mux determines if the clock signal feeding into the divider banks is the calculated VCO frequency or REF. There are two select muxes (DIV1SRC and DIV2SRC) and two divider banks (Divider Bank 1 and Divider Bank 2) used to determine this clock signal. The clock signal passing through DIV1SRC and DIV2SRC is referred to as DIV1CLK and DIV2CLK, respectively. The divider banks have four unique divider options available: /2, /3, /4, and /DIVxN. DIVxN is a variable that can be independently programmed (DIV1N and DIV2N) for each of the two divider banks. The minimum value of DIVxN is 4. The maximum value of DIVxN is 127. A value of DIVxN below 4 is not guaranteed to work properly. DIV1SRC is a single bit variable, controlled by register 0CH. The remaining seven bits of register 0CH determine the value of post divider DIV1N. DIV2SRC is a single bit variable, controlled by register 47H. The remaining seven bits of register 47H determine the value of post divider DIV2N. Register 0CH and 47H are defined in Table 9. Charge Pump Settings [40H(2..0)] The correct pump setting is important for PLL stability. Charge pump settings are controlled by bits (4..2) of register 40H, and are dependent on internal variable PB (see “PLL Frequency, P Counter[40H(1..0)], [41H(7..0)], [42H(7)]”). Table 10 on page 10 summarizes the proper charge pump settings, based on Ptotal. See Table 11 on page 10 for register 40H bit locations and values. Table 7. Input Load Capacitor Register Bit Settings Address D7 D6 D5 D4 D3 D2 D1 D0 13H CapLoad(7) CapLoad(6) CapLoad(5) CapLoad(4) CapLoad(3) CapLoad(2) CapLoad(1) CapLoad(0) Table 8. P Counter and Q Counter Register Definition Address D7 D6 D5 D4 D3 D2 D1 D0 40H 1 1 0 Pump(2) Pump(1) Pump(0) PB(9) PB(8) 41H PB(7)PB(6) PB(5)PB(4) PB(3)PB(2) PB(1)PB(0) 42H PO Q(6) Q(5) Q(4) Q(3) Q(2) Q(1) Q(0) Table 9. PLL Post Divider Options Address D7 D6 D5 D4 D3 D2 D1 D0 0CH DIV1SRC DIV1N(6) DIV1N(5) DIV1N(4) DIV1N(3) DIV1N(2) DIV1N(1) DIV1N(0) 47H DIV2SRC DIV2N(6) DIV2N(5) DIV2N(4) DIV2N(3) DIV2N(2) DIV2N(1) DIV2N(0) |
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