CY29352

Document Number: 38-07476 Rev. *C

Page 5 of 10

AC Parameters

Parameter[6]

Description

Condition

Min

Typ

Max

Unit

VCO frequency

200

–

400

MHz

Input frequency

2 feedback

100

–

200

MHz

4 feedback

50

–

100

6 feedback

33.33

–

66.67

8 feedback

25

–

50

12 feedback

16.67

–

33.33

Bypass mode (PLL_EN# = 1)

0

–

200

Input duty cycle

25

–

75

%

TCLK input rise and fall time

0.7 V to 1.7 V

–

–

1.0

ns

Maximum output frequency

2 output

100

–

200

MHz

4 output

50

–

100

6 output

33.33

–

66.67

8 output

25

–

50

12 output

16.67

–

33.33

DC

Output duty cycle

47

–

53

%

44

–

56

Output rise and fall times

0.6 V to 1.8 V

0.1

–

1.0

ns

include jitter

–100

–

100

ps

Output to output skew

Skew within bank

–

–

125

ps

Bank to bank skew

Banks at same voltage, same frequency

–

–

175

ps

Banks at same voltage, different frequency

–

–

225

Output disable time

–

–

8

ns

Output enable time

–

–

10

ns

BW

PLL closed loop bandwidth (–3 dB)

2 feedback

–

2

–

MHz

4 feedback

–

1–1.5

–

6 feedback

–

0.6

–

8 feedback

–

0.75

–

12 feedback

–

0.5

–

Cycle to cycle jitter

Same frequency

–

–

100

ps

Multiple frequencies

–

–

300

Period jitter

Same frequency

–

–

100

ps

Multiple frequencies

–

–

150

IO phase jitter

VCO < 300 MHz

–

150

–

ps

VCO > 300 MHz

–

100

–

Maximum PLL lock time

–

–

1

ms

Note

6. AC characteristics apply for parallel output termination of 50

by characterization and are not 100% tested.

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