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CY2308SXC-1H Datasheet(PDF) 6 Page - Cypress Semiconductor |
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CY2308SXC-1H Datasheet(HTML) 6 Page - Cypress Semiconductor |
6 / 18 page CY2308 Document Number: 38-07146 Rev. *M Page 6 of 18 Switching Characteristics for Commercial Temperature Devices Parameter [9] Name Test Conditions Min Typ Max Unit Fin Input frequency – 10 – 133.3 MHz t1 Output frequency 30 pF load 10 – 100 (-1, -2, -3, -4) 66.67 (-5H) MHz t1 Output frequency 20 pF load, -1H, -5H devices 10 – 133.3 (-1H) 66.67 (-5H) MHz t1 Output frequency 15 pF load, -1, -2, -3, -4 devices 10 – 133.3 MHz tPD Duty cycle [9] = t2 t1 (-1, -2, -3, -4, -1H, -5H) Measured at 1.4 V, FOUT = 66.66 MHz, 30 pF load 40.0 50.0 60.0 % tPD Duty cycle [9] = t2 t1 (-1, -2, -3, -4, -1H, -5H) Measured at 1.4 V, FOUT < 50 MHz, 15 pF load 45.0 50.0 55.0 % t3 Rise time [9] (-1, -2, -3, -4) Measured between 0.8 V and 2.0 V, 30 pF load – – 2.20 ns t3 Rise time [9] (-1, -2, -3, -4) Measured between 0.8 V and 2.0 V, 15 pF load – – 1.50 ns t3 Rise time [9] (-1H, -5H) Measured between 0.8 V and 2.0 V, 30 pF load – – 1.50 ns t4 Fall time [9] (-1, -2, -3, -4) Measured between 0.8 V and 2.0 V, 30 pF load – – 2.20 ns t4 Fall time [9] (-1, -2, -3, -4) Measured between 0.8 V and 2.0 V, 15 pF load – – 1.50 ns t4 Fall time [9] (-1H, -5H) Measured between 0.8 V and 2.0 V, 30 pF load – – 1.25 ns t5 Output to output skew on same Bank [9] (-1, -2, -3, -4) All outputs equally loaded – – 200 ps Output to output skew (-1H, -5H) All outputs equally loaded – – 200 ps Output Bank A to output Bank B skew (-1, -4, -5H) All outputs equally loaded – – 200 ps Output Bank A to output Bank B skew (-2, -3) All outputs equally loaded – – 400 ps t6 Delay, REF rising edge to FBK rising edge [9] Measured at VDD/2 – 0 ±250 ps t7 Device to device skew [9] Measured at VDD/2 on the FBK pins of devices – 0 700 ps t8 Output slew rate [9] Measured between 0.8 V and 2.0 V on -1H, -5H device using Test Circuit 2 1– – V/ns tJ Cycle to cycle Jitter [9] (-1, -1H, -4, -5H) Measured at 66.67 MHz, loaded outputs, 15 pF load –75 200 ps Measured at 66.67 MHz, loaded outputs, 30 pF load –– 200 ps Measured at 133.3 MHz, loaded outputs, 15 pF load –– 100 ps tJ Cycle to cycle Jitter [9] (-2, -3) Measured at 66.67 MHz, loaded outputs, 30 pF load –– 400 ps Measured at 66.67 MHz, loaded outputs, 15 pF load –– 400 ps tLOCK PLL lock time [9] Stable power supply, valid clocks presented on REF and FBK pins –– 1.0 ms Note 9. All parameters are specified with loaded outputs. [+] Feedback |
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