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CY29948AXIT Datasheet(PDF) 4 Page - Cypress Semiconductor

Part # CY29948AXIT
Description  2.5 V or 3.3 V, 200-MHz, 1:12 Clock Distribution Buffer
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Manufacturer  CYPRESS [Cypress Semiconductor]
Direct Link  http://www.cypress.com
Logo CYPRESS - Cypress Semiconductor

CY29948AXIT Datasheet(HTML) 4 Page - Cypress Semiconductor

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CY29948
Document Number: 38-07288 Rev. *E
Page 4 of 10
AC Parameters[6]
VDD = VDDC = 3.3 V ± 10% or 2.5 V ± 5%, over the specified operating range.
Parameter
Description
Conditions
Min
Typ
Max
Unit
Fmax
Input Frequency[7]
VDD = 3.3 V
200
MHz
VDD = 2.5 V
170
Tpd
PECL_CLK to Q Delay[7]
VDD = 3.3 V
4.0
8.0
ns
TCLK to Q Delay[7]
4.4
8.9
PECL_CLK to Q Delay[7]
VDD = 2.5 V
6.0
10.0
TCLK to Q Delay[7]
6.4
10.9
FoutDC
Output Duty Cycle[7, 8, 9]
Measured at VDD/2
45
55
%
tpZL, tpZH
Output Enable Time (all outputs)
2
10
ns
tpLZ, tpHZ
Output Disable Time (all outputs)
2
10
ns
Tskew
Output-to-Output Skew[7, 9]
150
250
ps
Tskew(pp)
Part-to-Part Skew[10]
PECL_CLK to Q
1.5
ns
TCLK to Q
2.0
Ts
Set-up Time[7, 11]
SYNC_OE to PECL_CLK
1.0
ns
SYNC_OE to TCLK
0.0
Th
Hold Time[7, 11]
PECL_CLK to SYNC_OE
0.0
ns
TCLK to SYNC_OE
1.0
Tr/Tf
Output Clocks Rise/Fall Time[9]
0.8 V to 2.0 V, VDD = 3.3 V
0.20
1.0
ns
0.6 V to 1.8 V, VDD = 2.5 V
0.20
1.3
Pulse
Generator
Z = 50 ohm
Zo = 50 ohm
VTT
Zo = 50 ohm
VTT
RT = 50 ohm
RT = 50 ohm
CY29948 DUT
Figure 2. LVCMOS_CLK CY29948 Test Reference for VCC = 3.3 V and VCC = 2.5 V
Notes
6. Parameters are guaranteed by design and characterization. Not 100% tested in production. All parameters specified with loaded outputs.
7. Outputs driving 50
 transmission lines.
8. 50% input duty cycle.
9. See Figure 2 and Figure 3 on page 5.
10. Part-to-Part skew at a given temperature and voltage.
11. Setup and hold times are relative to the falling edge of the input clock.
[+] Feedback


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